IP Library Granted Patent US 7,456,498
Granted Patent B2
US 7,456,498 · App. 11/506,680 · Granted Nov 25, 2008

Integrated circuit package and system interface

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Quick Facts
Patent No.
US 7,456,498
App. No.
11/506,680
Granted
Nov 25, 2008
Kind
B2
Abstract

A method for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can be connected to any AC ground such as VSS or VDD package planes. The fissures can also accommodate the ingress of an optical fiber, which allows for a direct interface with the transceivers. The direct optical fiber interface permits the removal of solder balls for high speed signal traces, with their respective vias. On-chip integrated LEDs or other similar light source transceivers can drive the high speed signal media. Selective deposition of low dielectric material can also improve the frequency response of high speed signal package traces.

Claims (27)

1. A method for enhancing the performance and extending the frequency range of integrated circuit packages, comprising:

adding a fissure to a Flip-Chip (FC) package in order to improve a cross talk performance of said FC package for high and low frequency ranges;

thereafter connecting said fissure to an AC ground; and

configuring a top wall of said fissure utilizing a heat spreader layer in order to form an improved IC package based on said FC package in association with said fissure and said top wall thereof.

2. The method of claim 1 , further comprising:

accommodating an ingress of an optical fiber with said fissure in order to provide for a direct interface of said optical fiber with a transceiver;

driving a high speed signal trace utilizing an on-chip integrated light emitting device; and

improving a frequency response of said high speed signal trace by selectively depositing a low dielectric material.

3. The method of claim 2 wherein said light emitting device comprises a light emitting diode (LED).

4. The method of claim 2 wherein said optical fiber permits a removal of at least one solder ball from said high speed signal trace.

5. The method of claim 2 wherein said high speed signal trace comprises said fissure.

6. The method of claim 1 wherein said fissure extends a frequency range of said FC package.

7. The method of claim 1 further comprising:

forming said fissure utilizing a conductive material in order to connect said fissure to said AC ground.

8. The method of claim 1 further comprising:

associating a loop coupling with said improved IC package, wherein at least one I/O connected to said improved IC package drives said loop coupling.

9. The method of claim 8 wherein said loop coupling comprises an input to waveguide associated with said improved IC package and wherein said waveguide joins another waveguide which is configured on a PCB.

10. A method for enhancing the performance and extending the frequency range of integrated circuit packages, comprising:

adding a fissure to a Flip-Chip (FC) package in order to improve a cross talk performance of said FC package for high and low frequency ranges;

thereafter connecting said fissure to an AC ground;

configuring a top wall of said fissure utilizing a heat spreader layer;

accommodating an ingress of an optical fiber with said fissure in order to provide for a direct interface of said optical fiber with a transceiver;

driving a high speed signal trace utilizing an on-chip integrated light emitting device; and

improving a frequency response of said high speed signal trace by selectively depositing a low dielectric material in order to form an improved IC package based on said FC package in association with said fissure and said top wall thereof.

11. The method of claim 10 further comprising:

associating a loop coupling with said improved IC package, wherein at least one I/O connected to said improved IC package drives said loop coupling.

12. The method of claim 11 wherein said loop coupling comprises an input to waveguide associated with said improved IC package and wherein said waveguide joins another waveguide which is configured on a PCB.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 18, 2006
From: GASPARIK, FRANTISEK; CALLICOTT, STEVE
To: LSI LOGIC CORPORATION
Reel/Frame 018196/0873 →