Superjunction trench device and method
View Patent ↗Semiconductor structures and methods are provided for a semiconductor device ( 40 ) employing a superjunction structure ( 41 ) and overlying trench ( 91 ) with embedded control gate ( 48 ). The method comprises, forming ( 52 - 6, 52 - 9 ) interleaved first ( 70 - 1, 70 - 2, 70 - 3, 70 - 4 , etc.) and second ( 74 - 1, 74 - 2, 74 - 3 , etc.) spaced-apart regions of first ( 70 ) and second ( 74 ) semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material ( 74 ) has a higher mobility for the same carrier type than the first semiconductor material ( 70 ), and providing ( 52 - 14 ) an overlying third semiconductor material ( 82 ) in which a trench ( 90, 91 ) is formed with sidewalls ( 913 ) having thereon a fourth semiconductor material ( 87 ) that has a higher mobility than the third material ( 82 ), adapted to carry current ( 50 ) between source regions ( 86 ), through the fourth ( 87 ) semiconductor material in the trench ( 91 ) and the second semiconductor material ( 74 ) in the device drift space ( 42 ) to the drain ( 56 ). In a further embodiment, the first ( 70 ) and third ( 82 ) semiconductor materials are relaxed materials and the second ( 74 ) and fourth ( 87 ) semiconductor materials are strained semiconductor materials.
1. A semiconductor device, comprising:
a superjunction structure having interleaved regions of first and second semiconductor materials of opposite conductivity type and first and second mobilities, wherein the first and second semiconductor materials are separated by substantially parallel PN junctions and terminated at a first end by a substrate region substantially perpendicular to the PN junctions, wherein the superjunction structure has a second end spaced apart from the first end and wherein the second mobility is higher than the first mobility for the same carrier type;
a body regions of a third semiconductor material of a third mobility, coupled to the second end and having an outer surface opposed to the second end;
a trench having sidewalls extending from the outer surface at least to the second end; and
a fourth material of a fourth mobility higher than the third mobility for the same type of carrier at least on the sidewalls, and communicating with the superjunction structure.
2. The device of claim 1 , wherein the first semiconductor material is a relaxed semiconductor material and the second semiconductor material is a strained semiconductor material.
3. The device of claim 2 , wherein the third semiconductor material is a relaxed semiconductor material and the fourth semiconductor material is a strained semiconductor material.
4. The device of claim 3 , wherein the first and third semiconductor materials comprise SiGe and the second and fourth material is substantially silicon with less than 5% Ge.
5. The device of claim 4 , wherein the first and third semiconductor materials comprise Si:Ge in the ratio of X fraction Si to Y fraction Ge where X:Y ratios are in the range of 60:40 to 95:05.
6. The device of claim 5 , wherein Si:Ge ratios are in the range of 70:30 to 90:10.
7. The device of claim 1 , wherein the substrate comprises a first substantially silicon region with a Si:Ge transition layer of varying composition located between the first substantially silicon region and the superjunction structure.
8. The device of claim 7 , wherein the transition has a composition next to the first substantially silicon region of substantially silicon and a composition next to the superjunction structure that substantially matches the composition of the first semiconductor material.
9. The device of claim 1 , further comprising a first dielectric material at least on the fourth material on the sidewalls of the trench, and in a bottom portion of the trench, a second dielectric material of lower capacitance per unit area than the first dielectric.
10. A trench-type semiconductor device embodying a superjunction structure, the device comprising:
first spaced-apart regions of a first semiconductor material having a first conductivity type and a first lattice constant;
second spaced-apart regions of a second semiconductor material interleaved with the first space-apart regions, and having a second different conductivity type and a second different lattice constant so that the second semiconductor material in the second regions is strained with respect to the first semiconductor material in the first regions and one or more PN junctions exists therebetween; and
a further region of substantially relaxed semiconductor material in contact with the first and second spaced-apart interleaved regions and having an outer surface,
a trench in the further region extending from the outer surface substantially to the first and second spaced-apart interleaved regions;
a strained semiconductor material on at least the side-walls of the trench;
a gate dielectric over the strained semiconductor material;
a gate in contact with the gate dielectric, spaced apart thereby from the strained semiconductor material; and
one or more source regions communicating with the strained semiconductor material and separated from the first and second spaced-apart interleaved regions by a portion of the strained semiconductor material.
11. The device of claim 10 , further comprising a substrate of a predetermined lattice constant having a principal surface and a graded semiconductor layer having an inner surface against the principal surface and an outer surface distant from the inner surface adapted to receive the first spaced-apart regions and having a lattice constant at the outer surface that substantially matches the first lattice constant so that the first semiconductor material of the first regions formed on a first part of the outer surface is substantially relaxed.
12. The device of claim 11 , wherein the lattice constant at the outer surface is different from the second lattice constant so that the second material of the second regions formed on a second part of the outer surface is strained.
13. The device of claim 10 , wherein the first semiconductor material comprises SiGe and the second semiconductor material comprises Si with less than 5% Ge.
14. The device of claim 13 , wherein the first semiconductor material comprises Si:Ge ratios in the range of about 60:40 to 95:05.
15. The device of claim 14 , wherein the first semiconductor material comprises Si:Ge ratios in the range of about 70:30 to 90:10.
16. The device of claim 15 , wherein the first semiconductor material comprises a Si:Ge ratios of about 80:20 to 85:15.
17. A semiconductor device formed on a substrate having an outer surface, the device comprising:
first spaced-apart semiconductor regions of a first conductivity type and first mobility formed on the outer surface of the substrate;
second semiconductor regions of a second opposite conductivity type and higher second mobility, interleaved with the first spaced-apart semiconductor regions on the outer surface of the substrate to form a superjunction structure;
a first conductivity type body region of a third semiconductor having a third mobility formed over the superjunction structure, communicating with the superjunction structure and having an outer surface;
a trench extending through the body region from the outer surface to communicate with the superjunction structure; and
a fourth semiconductor region of a fourth mobility higher than the third mobility formed at least on the trench sidewalls.
18. The device of claim 17 , further comprising a gate dielectric in contact with the fourth semiconductor region.
19. The device of claim 18 , further comprising a gate within the trench separated from the fourth semiconductor material by the gate dielectric.
20. The device of claim 19 , further comprising one or more source regions within the body region in contact with the fourth semiconductor region and separated from the superjunction structure by a portion of the fourth semiconductor region.
21. The device of claim 17 further comprising a buffer layer displaced between the substrate and the first and second semiconductor regions.
22. The device of claim 21 wherein the buffer layer is configured to provide a transition zone from the substrate to the first and second semiconductor regions.