Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
View Patent ↗A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
1. A differential input/output cell for a field programmable gate array comprising:
a first input line;
a second input line;
a first output line;
a second output line;
a first input/output line coupled to a first input/output pad;
a second input/output line coupled to a second input/output pad;
a first differential amplifier having a non-inverting input coupled to the first input/output line, an inverting input coupled to one of a reference voltage and the second input/output line, and an output;
a first input multiplexer having a first data input coupled to the first input/output line, a second data input coupled to the output of the first differential amplifier, a control input, and an output;
a first input delay multiplexer having a first data input coupled to the output of the first input multiplexer, a second data input coupled to the output of the first input multiplexer through a delay element, a control input, and an output coupled to the first input line;
a second differential amplifier having a non-inverting input coupled to the second input/output line, an inverting input coupled to the reference voltage, and an output;
a second input multiplexer having a first data input coupled to the second input/output line, a second data input coupled to the output of the second differential amplifier, a control input, and an output;
a second input delay multiplexer having a first data input coupled to the output of the second input multiplexer, a second data input coupled to the output of the second input multiplexer through a delay element, a control input, and an output coupled to the second input line;
a first output buffer;
a second output buffer;
a first output multiplexer having a first data input connected to the first output line, a second input connected to the first output line through a delay element, a control input, and an output coupled to the input of the first output buffer;
a second output multiplexer having a first data input connected to the second output line, a second input connected to the first output line through an inverter, a control input, and an output coupled to the input of the second output buffer; and
programmable elements coupled to the control inputs of the first and second input multiplexers, the first and second input delay multiplexers, and the first and second output multiplexers to select between signals at the first data inputs and the second data inputs of the first and second input multiplexers, the first and second input delay multiplexers, and the first and second output multiplexers.
2. The differential input/output cell of claim 1 wherein:
the first output buffer includes an enable input coupled to a first output-enable line; and
the second output buffer includes an enable input coupled to a second output-enable line.
3. The differential input/output cell of claim 1 further including a boundary scan register coupled between the first output-enable line and the enable input of the first output buffer, between the second output-enable line and the enable input of the second output buffer, between the output of the first output multiplexer and the input of the first output buffer, between the output of the second output multiplexer and the input of the second output buffer, between the output of the first input delay multiplexer and the first input line, and between the output of the second input delay multiplexer and the second input line.
4. The differential input/output cell of claim 1 wherein the inverting input of the first differential amplifier is coupled to the reference voltage.
5. The differential input/output cell of claim 1 wherein the inverting input of the first differential amplifier is coupled to the second input/output line.
6. The differential input/output cell of claim 1 wherein:
the first input line provides an input signal to programmable circuitry;
the second input line provides an input signal to the programmable circuitry;
the first output line provides an output signal from the programmable circuitry;
the second output line provides an output signal from the programmable circuitry;
the first output-enable line provides an enable signal from the programmable circuitry; and
the second output-enable line provides an enable signal from the programmable circuitry.