Programmable multiplexer
An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A 1 , A 2 , A 3 , A 4 ). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A 1 , A 2 , . . . , A j , where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.
1. A method for configuring a programmable logic device to emulate a conventional multiplexer by using a multiplexer having m input ports, wherein the conventional multiplexer has j input ports accepting respective fixed logical values A 1 , A 2 , A 3 , . . . , A j and also has k select ports for coupling to k variable signals I 1 , . . . , I k , where m=j/2, the method comprising:
providing the fixed logical values A 1 , A 2 , A 3 , . . . , A j ; and
selecting a signal from (1) a logical low, (2) a logical high, (3) the first variable signal I 1 and (4) a complement of the first variable signal I 1 , based on the fixed logical values A 1 , A 2 , A 3 , . . . , A j , for each of m signals D 1 , . . . , D m .
2. The method of claim 1 , further comprising programming a plurality of switches for providing the m selected signals D 1 , . . . , D m to the m input ports of the multiplexer.
3. The method of claim 1 , further comprising programming one or more switches for coupling the k−1 variable signals I 2 , . . . , I k to n corresponding select input ports S 1 , . . . , S n of the m data input multiplexer, where n=k−1.
4. The method of claim 1 , further comprising applying the variable signals I 1 , . . . , I k in the programmable logic device.
5. The method of claim 1 , further comprising:
coupling an output signal of the multiplexer to an input port of a register; and
applying a clock signal to the register to hold the output signal at an output port of the register.
6. The method of claim 1 , wherein k=2, j=4 and m=2.
7. The method of claim 1 , wherein k=3, j=8 and m=4.
8. The method of claim 1 , wherein k=4, j=16 and m=8.