IP Library Assignment 075567/0964
Patent Assignment
Reel/Frame 075567/0964

Release of Security Interest

Recorded: 2026-05-07 Pages: 10
Assignor
HERITAGE BANK OF COMMERCE
Executed: 2026-05-01
Assignee
QUICKLOGIC CORPORATION
2220 LUNDY AVE., SAN JOSE, CALIFORNIA, 95131
Covered Properties (116)
Sectional Configuration for Programmable Logic Devices
Application: 18/307,699 →
Publication: US US20230353156A1
Heart Rate Monitor
Application: 16/601,116 →
Publication: US US20200037905A1
Method and Apparatus for Programming Anti-Fuse Devices
Patent: 5,294,846 →
Application: 07/931,048 →
Configuration Latch for Programmable Logic Device
Application: 17/697,856 →
Publication: US US20230299773A1
Area-Efficient Configuration Latch for Programmable Logic Device
Application: 17/725,564 →
Publication: US US20230343372A1
Programmable Logic Device with Design for Test Functionality
Application: 17/714,136 →
Publication: US US20230317192A1
Sectional Configuration for Programmable Logic Devices
Application: 17/697,862 →
Method and Apparatus for Implementing an Internal Tri-State Bus Within a Programmable Logic Circuit
Patent: 5,773,994 →
Application: 08/573,237 →
Programmable I/O Cell with Data Conversion Capability
Patent: 5,760,719 →
Application: 08/580,836 →
Architecture for Fpgas
Patent: 5,656,949 →
Application: 08/581,064 →
Planar Antifuse and Method of Fabrication
Patent: 5,573,971 →
Application: 08/580,938 →
Programmable I/O Cell with Data Conversion Capability
Patent: 5,786,710 →
Application: 08/581,105 →
Regulator with Variable Capacitor for Stability Compensation
Patent: 7,088,082 →
Application: 10/738,382 →
Publication: US US20050127885A1
Programmable I/O Cell with Data Conversion Capability
Patent: 5,869,982 →
Application: 08/580,770 →
Method of Making an Antifuse Metal Post Structure
Patent: 5,693,556 →
Application: 08/581,032 →
Programming Architecture for a Programmable Integrated Circuit Employing Antifuses
Patent: 5,825,201 →
Application: 08/667,702 →
Programmable I/O Cell with Data Conversion Capability
Patent: 5,917,337 →
Application: 08/578,201 →
Programmable I/O Cell with Data Conversion Capability
Patent: 5,811,989 →
Application: 08/967,435 →
Method for Fabrication of Programmable Interconnect Structure
Patent: 5,989,943 →
Application: 07/447,969 →
Programming of Antifuses
Patent: 5,243,226 →
Application: 07/739,076 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,557,136 →
Application: 07/892,466 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,362,676 →
Application: 07/920,971 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,280,202 →
Application: 08/024,986 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,416,367 →
Application: 08/189,352 →
Select Set-Based Technology Mapping Method and Apparatus
Patent: 5,526,276 →
Application: 08/231,595 →
Field Programmable Antifuse Device and Programming Method Therefor
Patent: 5,469,077 →
Application: 08/263,985 →
Intergated Circuit Facilitating Simultaneous Programming of Multiple Antifuses
Patent: 5,495,181 →
Application: 08/349,093 →
Programmable Application Specific Integrated Circuit Using Logic Circuits to Program Antifuses Therein
Patent: 5,477,167 →
Application: 08/379,061 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,594,364 →
Application: 08/493,981 →
Reducing Propagation Delays in a Programmable Device
Patent: 5,729,468 →
Application: 08/520,441 →
Electrically Programmable Interconnect Structure Having a Pecvd Amorphous Silicon Element
Patent: 5,780,919 →
Application: 08/646,823 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Routing Resources
Patent: 5,925,920 →
Application: 08/662,056 →
Security Antifuse That Prevents Readout of Some but Not Other Information from a Programmed Field Programmable Gate Array
Patent: 5,898,776 →
Application: 08/754,461 →
Three-Statable Net Driver for Antifuse Field Programmable Gate Array
Patent: 6,028,444 →
Application: 08/771,471 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent: 5,892,684 →
Application: 08/892,304 →
Programmable Integrated Circuit Having a Routing Conductor That Is Driven with Programming Current from Two Different Programming Voltage Terminals
Patent: 6,011,408 →
Application: 08/931,870 →
Programmable Integrated Circuit Having Parallel Routing Conductors Coupled to Programming Drivers in Different Locations
Patent: 6,018,251 →
Application: 08/931,896 →
Programmable Integrated Circuit Having L-Shaped Programming Power Buses That Extend Along Sides of the Integrated Circuit
Patent: 5,986,469 →
Application: 08/932,890 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 6,097,077 →
Application: 09/075,493 →
Field Programmable Gate Array Having Internal Logic Transistors with Two Different Gate Insulator Thicknesses
Patent: 6,127,845 →
Application: 09/112,700 →
Programming Architecture for Field Programmable Gate Array
Patent: 6,169,416 →
Application: 09/145,581 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Routing Resources
Patent: 6,237,131 →
Application: 09/301,685 →
Precharge Circuitry in Ram Circuit
Patent: 6,097,651 →
Application: 09/345,971 →
Techniques and circuits for high yield improvements in programmable devices using redundant logic
Patent: 6,347,378 →
Application: 09/556,772 →
Architecture for Field Programmable Gate Array
Patent: 6,426,649 →
Application: 09/751,440 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,122,685 →
Application: 07/665,103 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,220,213 →
Application: 07/847,137 →
Field Programmable Antifuse Device and Programming Method Therefor
Patent: 5,327,024 →
Application: 07/907,904 →
Method of Determining an Electrical Characteristic of an Antifuse and Apparatus Therefor
Patent: 5,293,133 →
Application: 07/937,071 →
Programming of Antifuses
Patent: 5,397,939 →
Application: 08/094,677 →
Method and Apparatus for Programming Anti-Fuse Devices
Patent: 5,448,184 →
Application: 08/210,000 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,430,390 →
Application: 08/245,309 →
Field Programmable Gate Array Having Reproducible Metal-to-Metal Amorphous Silicon Antifuses
Patent: 5,717,230 →
Application: 08/323,168 →
Bond Pad Having Vias Usable with Antifuse Process Technology
Patent: 6,300,688 →
Application: 08/350,865 →
Method and Apparatus for Programming Anti-Fuse Devices
Patent: 5,469,109 →
Application: 08/385,800 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent: 5,654,649 →
Application: 08/501,644 →
Integrated Circuit Facilitating Simultaneous Programming of Multiple Antifuses
Patent: 5,600,262 →
Application: 08/540,726 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,701,027 →
Application: 08/651,102 →
Interface Cell for a Programmable Integrated Circuit Employing Antifuses
Patent: 5,900,742 →
Application: 08/667,783 →
Logic Module for Field Programmable Gate Array
Patent: 5,682,106 →
Application: 08/755,758 →
Power-Up Circuit for Field Programmable Gate Arrays
Patent: 5,828,538 →
Application: 08/775,984 →
Method for Forming Programmable Interconnect Structures and Program- Mable Intergrated Circuits
Patent: 5,786,268 →
Application: 08/904,387 →
Field Programmable Gate Array Having Testable Antifuse Programming Architecture and Methods Therefor
Patent: 6,081,129 →
Application: 08/931,893 →
Programmable Integrated Circuit Having Shared Programming Conductors Between Columns of Logic Modules
Patent: 6,084,428 →
Application: 08/931,897 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,986,468 →
Application: 08/988,432 →
Protection of Logic Modules in a Field Programmable Gate Array During Antifuse Programming
Patent: 6,157,207 →
Application: 09/076,367 →
Metal-To-Metal Antifuse Having Improved Barrier Layer
Patent: 6,107,165 →
Application: 09/133,998 →
Charge Pumps of Antifuse Programming Circuitry Powered from High Voltage Compatibility Terminal
Patent: 6,140,837 →
Application: 09/161,192 →
Programmable Device Having Antifuses Without Programmable Material Edges and/or Corners Underneath Metal
Patent: 6,154,054 →
Application: 09/309,165 →
Method for Fabrication of Programmable Interconnect Structure
Patent: 6,150,199 →
Application: 09/405,979 →
Programmable Antifuse Intefacing a Programmable Logic and a Dedicated Device
Patent: 6,552,410 →
Application: 09/650,773 →
Configurable Computational Unit Embedded in a Programmable Device
Patent: 6,483,343 →
Application: 09/751,538 →
Programming of Antifuses
Patent: 5,302,546 →
Application: 07/738,707 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,196,724 →
Application: 07/874,983 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,319,238 →
Application: 07/920,734 →
Programmed Programmable Device and Method for Programming Antifuses of a Programmable Device
Patent: 5,544,070 →
Application: 07/937,331 →
Electrically Programmable Interconnect Structure Having a Pecvd Amorphous Silicon Element
Patent: 5,502,315 →
Application: 08/161,504 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,396,127 →
Application: 08/222,726 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent: 5,424,655 →
Application: 08/246,527 →
Method for Simultaneous Programming of Multiple Antifuses
Patent: 5,552,720 →
Application: 08/349,092 →
Programming of Antifuses
Patent: 5,471,154 →
Application: 08/372,611 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,587,669 →
Application: 08/399,117 →
Estimating Propagation Delays in a Programmable Device
Patent: 5,675,502 →
Application: 08/517,871 →
Reducing Programming Time of a Field Programmable Gate Array Employing Antifuses
Patent: 5,661,412 →
Application: 08/541,662 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Logic
Patent: 6,148,390 →
Application: 08/662,054 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 5,726,586 →
Application: 08/744,225 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent: 5,880,512 →
Application: 08/768,601 →
Clock Network for Field Programmable Gate Array
Patent: 5,892,370 →
Application: 08/781,985 →
Programming Architecture for a Programmable Integrated Circuit Employing Test Antifuses and Test Transistors
Patent: 5,966,028 →
Application: 08/929,654 →
Supplying Antifuse Programming Current Onto a Long Wire Segment of a Programmable Device from Two Different Programming Conductors
Patent: 5,859,543 →
Application: 08/931,895 →
Programmable Integrated Circuit Having a Test Circuit for Testing the Integrity of Routing Resource Structures
Patent: 6,130,554 →
Application: 08/932,390 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent: 6,078,191 →
Application: 09/038,728 →
Power-Up Circuit for Field Programmable Gate Arrays
Patent: 6,101,074 →
Application: 09/094,462 →
Programmable Device Having Antifuses Without Programmable Material Edges and/or Corners Underneath Metal
Patent: 5,955,751 →
Application: 09/133,999 →
Metal-To-Metal Antifuse with Non-Conductive Diffusion Barrier
Patent: 6,515,343 →
Application: 09/196,946 →
Virtual Programmable Device and Method of Programming
Patent: 6,188,242 →
Application: 09/343,980 →
Programmable Device with an Embedded Portion for Receiving a Standard Circuit Design
Patent: 6,519,753 →
Application: 09/451,681 →
Method of Forming a Metal-to-Metal Antifuse with Non-Conductive Diffusion Barrier
Patent: 6,509,209 →
Application: 09/697,706 →
Method of Programming an Antifuse
Patent: 7,187,228 →
Application: 09/887,834 →
Serializer/Deserializer Embedded in a Programmable Device
Patent: 6,542,096 →
Application: 09/939,533 →
Publication: US US20030039168A1
Programmable Multiplexer
Patent: 7,482,834 →
Application: 11/551,201 →
Publication: US US20080094103A1
Dynamic Clock Control
Patent: 7,443,222 →
Application: 11/753,531 →
Assigning Operational Codes To Lists of Values of Control Signals Selected From A Processor Design Based On End-User Software
Patent: 9,811,335 →
Application: 14/053,393 →
Multiple Axis Wrist Worn Pedometer
Application: 14/602,188 →
Publication: US US20160209232A1
Sensor Hub Batch Packing
Application: 15/163,474 →
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Differential Charge Pump
Patent: 7,184,510 →
Application: 10/672,798 →
Publication: US US20050185746A1
Low Power Mode
Patent: 7,646,216 →
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Publication: US US20080122483A1
Phy-Less Ulpi and Utmi Bridges
Patent: 8,261,002 →
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Publication: US US20090070515A1
Logic Cell for Programmable Logic Device
Patent: 9,287,868 →
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Publication: US US20160065213A1
Local Routing Network with Selective Fast Paths for Programmable Logic Device
Patent: 9,628,083 →
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Publication: US US20170099052A1
Switchable Power Islands Having Configurably on Routing Paths
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Publication: US US20180269879A1
Adjustable Interface Buffer Circuit Between a Programmable Logic Device and a Dedicated Device
Patent: 8,018,248 →
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Publication: US US20080074141A1
Fpga Programming Structure for Atpg Test Coverage
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Adjustable Interface Buffer Circuit Between a Programmable Logic Device and a Dedicated Device
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Routing Network for Programmable Logic Device
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Heart Rate Monitor
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Publication: US US20170020398A1
Related Assignments (25)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest. Dec 8, 1989
From: CHAN, ANDREW K.
To: PEER RESEARCH, INC.
Reel/Frame 005209/0213 →
Assignment of Assignors Interest. Dec 8, 1989
From: WHITTEN, RALPH G.; BECHTEL, RICHARD L.; THOMAS, MAMMEN
To: PEER RESEARCH, INC.
Reel/Frame 005209/0211 →
Change of Name Feb. 14, 1991 Mar 19, 1991
From: PEER RESEARCH, INC., A CORP. OF CA
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 005639/0251 →
Assignment of Assignors Interest. Jul 31, 1991
From: CHAN, ANDREW K.
To: QUIKCLOGIC CORPORATION
Reel/Frame 005806/0422 →
Assignment of Assignors Interest. Jun 2, 1992
From: GORDON, KATHRYN E.; WONG, RICHARD J.
To: QUICKLOGIC CORPORATION
Reel/Frame 006153/0730 →
Assignment of Assignor's Interest Jan 24, 1994
From: PAIVINEN, JOHN O.
To: QUICKLOGIC CORPORATION
Reel/Frame 006838/0152 →
Change of Name May 19, 1995
From: PEER RESEARCH, INC.
To: QUICKLOGIC CORPORATION
Reel/Frame 007516/0737 →
Security Agreement Oct 19, 1995
From: QUICKLOGIC CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 007696/0480 →
Assignment of Assignor's Interest Dec 15, 1995
From: JONES, CHRISTOPHER W.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007802/0046 →
Assignment of Assignor's Interest Dec 29, 1995
From: GRAF, W. ALFRED
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007858/0655 →
Assignment of Assignor's Interest Dec 29, 1995
From: GRAF, W. ALFRED
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007832/0427 →
Assignment of Assignor's Interest Dec 29, 1995
From: GRAF, W. ALFRED
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007814/0963 →
Assignment of Assignor's Interest Dec 29, 1995
From: GRAF, W. ALFRED
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007811/0511 →
Assignment of Assignor's Interest Mar 15, 1996
From: YIP, AARON S.; LACEY, TIMOTHY M.; NAYAK, ANUP K.; NEMA, RAJIV
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007994/0460 →
Assignment of Assignor's Interest Mar 20, 1996
From: CLEEVES, JAMES M.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007853/0930 →
Assignment of Assignor's Interest Mar 20, 1996
From: CLEEVES, JAMES M.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 007852/0405 →
Assignment of Assignor's Interest Jun 21, 1996
From: KOLZE, PAIGE A.; CHAN, ANDREW K.; EATON, DAVID D.; APLAND, JAMES M.
To: QUICKLOGIC, CORPORATION
Reel/Frame 008062/0120 →
Assignment of Assignor's Interest Jun 21, 1996
From: LEBBY, MICHAEL S.; JACHIMOWICZ, KAREN E.; JIANG, WENBIN
To: MOTOROLA, INC.
Reel/Frame 008069/0577 →
Release of Security Agreement Jul 1, 1996
From: QUICK LOGIC CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 008018/0367 →
Assignment of Assignor's Interest Aug 20, 1998
From: CYPRESS SEMICONDUCTOR CORPORATION
To: QUICKLOGIC CORPORATION
Reel/Frame 009407/0115 →
Notice of Disputed Ownership Sep 14, 1998
From: CYPRESS SEMICONDUCTOR CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 009932/0155 →
Notice of Disputed Ownership May 3, 1999
From: CYPRESS SEMICONDUCTOR CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 009941/0298 →
Notice of Disputed Ownership May 3, 1999
From: CYPRESS SEMICONDUCTOR CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 009922/0776 →
Notice of Disputed Ownership May 3, 1999
From: CYPRESS SEMICONDUCTOR CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 009922/0842 →
Notice of Disputed Ownership May 3, 1999
From: CYPRESS SEMICONDUCTOR CORPORATION
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 009942/0674 →