Patent Assignment
Reel/Frame 047198/0960
Security Interest
Recorded: 2018-10-05
Pages: 12
Assignor
QUICKLOGIC CORPORATION
Executed: 2018-09-28
Assignee
HERITAGE BANK OF COMMERCE
150 SOUTH ALMADEN BLVD., ATTN: MIKE HANSEN, SAN JOSE, CALIFORNIA, 95113
Covered Properties
(98)
Method for Fabrication of Programmable Interconnect Structure
Patent:
5,989,943 →
Application:
07/447,969 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,122,685 →
Application:
07/665,103 →
Programming of Antifuses
Patent:
5,302,546 →
Application:
07/738,707 →
Programming of Antifuses
Patent:
5,243,226 →
Application:
07/739,076 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,220,213 →
Application:
07/847,137 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,196,724 →
Application:
07/874,983 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,557,136 →
Application:
07/892,466 →
Field Programmable Antifuse Device and Programming Method Therefor
Patent:
5,327,024 →
Application:
07/907,904 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,319,238 →
Application:
07/920,734 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,362,676 →
Application:
07/920,971 →
Method of Determining an Electrical Characteristic of an Antifuse and Apparatus Therefor
Patent:
5,293,133 →
Application:
07/937,071 →
Programmed Programmable Device and Method for Programming Antifuses of a Programmable Device
Patent:
5,544,070 →
Application:
07/937,331 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,280,202 →
Application:
08/024,986 →
Programming of Antifuses
Patent:
5,397,939 →
Application:
08/094,677 →
Electrically Programmable Interconnect Structure Having a Pecvd Amorphous Silicon Element
Patent:
5,502,315 →
Application:
08/161,504 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,416,367 →
Application:
08/189,352 →
Method and Apparatus for Programming Anti-Fuse Devices
Patent:
5,448,184 →
Application:
08/210,000 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,396,127 →
Application:
08/222,726 →
Select Set-Based Technology Mapping Method and Apparatus
Patent:
5,526,276 →
Application:
08/231,595 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,430,390 →
Application:
08/245,309 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent:
5,424,655 →
Application:
08/246,527 →
Field Programmable Antifuse Device and Programming Method Therefor
Patent:
5,469,077 →
Application:
08/263,985 →
Field Programmable Gate Array Having Reproducible Metal-to-Metal Amorphous Silicon Antifuses
Patent:
5,717,230 →
Application:
08/323,168 →
Method for Simultaneous Programming of Multiple Antifuses
Patent:
5,552,720 →
Application:
08/349,092 →
Intergated Circuit Facilitating Simultaneous Programming of Multiple Antifuses
Patent:
5,495,181 →
Application:
08/349,093 →
Bond Pad Having Vias Usable with Antifuse Process Technology
Patent:
6,300,688 →
Application:
08/350,865 →
Programming of Antifuses
Patent:
5,471,154 →
Application:
08/372,611 →
Programmable Application Specific Integrated Circuit Using Logic Circuits to Program Antifuses Therein
Patent:
5,477,167 →
Application:
08/379,061 →
Method and Apparatus for Programming Anti-Fuse Devices
Patent:
5,469,109 →
Application:
08/385,800 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,587,669 →
Application:
08/399,117 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,594,364 →
Application:
08/493,981 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent:
5,654,649 →
Application:
08/501,644 →
Estimating Propagation Delays in a Programmable Device
Patent:
5,675,502 →
Application:
08/517,871 →
Reducing Propagation Delays in a Programmable Device
Patent:
5,729,468 →
Application:
08/520,441 →
Integrated Circuit Facilitating Simultaneous Programming of Multiple Antifuses
Patent:
5,600,262 →
Application:
08/540,726 →
Reducing Programming Time of a Field Programmable Gate Array Employing Antifuses
Patent:
5,661,412 →
Application:
08/541,662 →
Electrically Programmable Interconnect Structure Having a Pecvd Amorphous Silicon Element
Patent:
5,780,919 →
Application:
08/646,823 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,701,027 →
Application:
08/651,102 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Logic
Patent:
6,148,390 →
Application:
08/662,054 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Routing Resources
Patent:
5,925,920 →
Application:
08/662,056 →
Interface Cell for a Programmable Integrated Circuit Employing Antifuses
Patent:
5,900,742 →
Application:
08/667,783 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,726,586 →
Application:
08/744,225 →
Security Antifuse That Prevents Readout of Some but Not Other Information from a Programmed Field Programmable Gate Array
Patent:
5,898,776 →
Application:
08/754,461 →
Logic Module for Field Programmable Gate Array
Patent:
5,682,106 →
Application:
08/755,758 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
5,880,512 →
Application:
08/768,601 →
Three-Statable Net Driver for Antifuse Field Programmable Gate Array
Patent:
6,028,444 →
Application:
08/771,471 →
Power-Up Circuit for Field Programmable Gate Arrays
Patent:
5,828,538 →
Application:
08/775,984 →
Clock Network for Field Programmable Gate Array
Patent:
5,892,370 →
Application:
08/781,985 →
Programmable Application Specific Integrated Circuit Employing Antifuses and Methods Therefor
Patent:
5,892,684 →
Application:
08/892,304 →
Method for Forming Programmable Interconnect Structures and Program- Mable Intergrated Circuits
Patent:
5,786,268 →
Application:
08/904,387 →
Programming Architecture for a Programmable Integrated Circuit Employing Test Antifuses and Test Transistors
Patent:
5,966,028 →
Application:
08/929,654 →
Programmable Integrated Circuit Having a Routing Conductor That Is Driven with Programming Current from Two Different Programming Voltage Terminals
Patent:
6,011,408 →
Application:
08/931,870 →
Field Programmable Gate Array Having Testable Antifuse Programming Architecture and Methods Therefor
Patent:
6,081,129 →
Application:
08/931,893 →
Supplying Antifuse Programming Current Onto a Long Wire Segment of a Programmable Device from Two Different Programming Conductors
Patent:
5,859,543 →
Application:
08/931,895 →
Programmable Integrated Circuit Having Parallel Routing Conductors Coupled to Programming Drivers in Different Locations
Patent:
6,018,251 →
Application:
08/931,896 →
Programmable Integrated Circuit Having Shared Programming Conductors Between Columns of Logic Modules
Patent:
6,084,428 →
Application:
08/931,897 →
Programmable Integrated Circuit Having a Test Circuit for Testing the Integrity of Routing Resource Structures
Patent:
6,130,554 →
Application:
08/932,390 →
Programmable Integrated Circuit Having L-Shaped Programming Power Buses That Extend Along Sides of the Integrated Circuit
Patent:
5,986,469 →
Application:
08/932,890 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
5,986,468 →
Application:
08/988,432 →
Programmable Application Specific Integrated Circuit and Logic Cell Therefor
Patent:
6,078,191 →
Application:
09/038,728 →
Programmable Interconnect Structures and Programmable Integrated Circuits
Patent:
6,097,077 →
Application:
09/075,493 →
Protection of Logic Modules in a Field Programmable Gate Array During Antifuse Programming
Patent:
6,157,207 →
Application:
09/076,367 →
Power-Up Circuit for Field Programmable Gate Arrays
Patent:
6,101,074 →
Application:
09/094,462 →
Field Programmable Gate Array Having Internal Logic Transistors with Two Different Gate Insulator Thicknesses
Patent:
6,127,845 →
Application:
09/112,700 →
Metal-To-Metal Antifuse Having Improved Barrier Layer
Patent:
6,107,165 →
Application:
09/133,998 →
Programmable Device Having Antifuses Without Programmable Material Edges and/or Corners Underneath Metal
Patent:
5,955,751 →
Application:
09/133,999 →
Programming Architecture for Field Programmable Gate Array
Patent:
6,169,416 →
Application:
09/145,581 →
Charge Pumps of Antifuse Programming Circuitry Powered from High Voltage Compatibility Terminal
Patent:
6,140,837 →
Application:
09/161,192 →
Metal-To-Metal Antifuse with Non-Conductive Diffusion Barrier
Patent:
6,515,343 →
Application:
09/196,946 →
Techniques and Circuits for High Yield Improvements in Programmable Devices Using Redundant Routing Resources
Patent:
6,237,131 →
Application:
09/301,685 →
Programmable Device Having Antifuses Without Programmable Material Edges and/or Corners Underneath Metal
Patent:
6,154,054 →
Application:
09/309,165 →
Virtual Programmable Device and Method of Programming
Patent:
6,188,242 →
Application:
09/343,980 →
Precharge Circuitry in Ram Circuit
Patent:
6,097,651 →
Application:
09/345,971 →
Method for Fabrication of Programmable Interconnect Structure
Patent:
6,150,199 →
Application:
09/405,979 →
Programmable Device with an Embedded Portion for Receiving a Standard Circuit Design
Patent:
6,519,753 →
Application:
09/451,681 →
Techniques and circuits for high yield improvements in programmable devices using redundant logic
Patent:
6,347,378 →
Application:
09/556,772 →
Programmable Antifuse Intefacing a Programmable Logic and a Dedicated Device
Patent:
6,552,410 →
Application:
09/650,773 →
Method of Forming a Metal-to-Metal Antifuse with Non-Conductive Diffusion Barrier
Patent:
6,509,209 →
Application:
09/697,706 →
Architecture for Field Programmable Gate Array
Patent:
6,426,649 →
Application:
09/751,440 →
Configurable Computational Unit Embedded in a Programmable Device
Patent:
6,483,343 →
Application:
09/751,538 →
Method of Programming an Antifuse
Patent:
7,187,228 →
Application:
09/887,834 →
Serializer/Deserializer Embedded in a Programmable Device
Differential Charge Pump
Adjustable Interface Buffer Circuit Between a Programmable Logic Device and a Dedicated Device
Programmable Multiplexer
Low Power Mode
Fpga Programming Structure for Atpg Test Coverage
Dynamic Clock Control
Patent:
7,443,222 →
Application:
11/753,531 →
Phy-Less Ulpi and Utmi Bridges
Adjustable Interface Buffer Circuit Between a Programmable Logic Device and a Dedicated Device
Assigning Operational Codes To Lists of Values of Control Signals Selected From A Processor Design Based On End-User Software
Patent:
9,811,335 →
Application:
14/053,393 →
Logic Cell for Programmable Logic Device
Routing Network for Programmable Logic Device
Patent:
9,118,325 →
Application:
14/476,518 →
Multiple Axis Wrist Worn Pedometer
Local Routing Network with Selective Fast Paths for Programmable Logic Device
Heart Rate Monitor
Sensor Hub Batch Packing
Switchable Power Islands Having Configurably on Routing Paths
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignors Interest.
Dec 8, 1989
From: WHITTEN, RALPH G.; BECHTEL, RICHARD L.; THOMAS, MAMMEN
To: PEER RESEARCH, INC.
Reel/Frame 005209/0211 →
Assignment of Assignors Interest.
Dec 8, 1989
From: CHAN, ANDREW K.
To: PEER RESEARCH, INC.
Reel/Frame 005209/0213 →
Assignment of Assignors Interest.
Mar 6, 1991
From: CHAN, ANDREW K.; BIRKNER, JOHN M.; CHUA, HUA-THYE
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 005629/0433 →
Change of Name Feb. 14, 1991
Mar 19, 1991
From: PEER RESEARCH, INC., A CORP. OF CA
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 005639/0251 →
Assignment of Assignors Interest.
Jul 31, 1991
From: CHAN, ANDREW K.
To: QUIKCLOGIC CORPORATION
Reel/Frame 005806/0422 →
Assignment of Assignors Interest.
Jul 31, 1991
From: GORDON, KATHRYN E.; CHAN, ANDREW K.
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 005802/0072 →
Assignment of Assignors Interest.
Jun 2, 1992
From: GORDON, KATHRYN E.; WONG, RICHARD J.
To: QUICKLOGIC CORPORATION
Reel/Frame 006153/0730 →
Assignment of Assignors Interest.
Jul 2, 1992
From: COX, WILLIAM D.
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 006181/0200 →
Assignment of Assignors Interest.
Aug 27, 1992
From: COX, WILLIAM D.; CHAN, ANDREW K. L.; WONG, RICHARD J.; APLAND, JAMES M.
To: QUICKLOGIC CORPORATION, A CORP. OF CA
Reel/Frame 006257/0775 →
Assignment of Assignors Interest.
Oct 14, 1992
From: BIRKNER, JOHN M.; MARTIN, DAVID T.; WONG, RICHARD J.
To: QUICKLOGIC CORPORATION
Reel/Frame 006274/0522 →
Assignment of Assignor's Interest
Jan 31, 1994
From: CHAN, ANDREW K.; BIRKNER, JOHN M.; CHUA, HUA THYE; COX, WILLIAM D.
To: QUICKLOGIC CORPORATION
Reel/Frame 006872/0688 →
Assignment of Assignor's Interest
May 20, 1994
From: CHUA, HUA-THYE
To: QUICKLOGIC CORPORATION
Reel/Frame 007008/0853 →
Assignment of Assignor's Interest
Jun 24, 1994
From: COX, WILLIAM D.; LEHMANN, ERIC E.; LULLA, MUKESH T.; NATHAMUNI, VANKATESH R.
To: QUICKLOGIC CORPORATION
Reel/Frame 007178/0086 →
Assignment of Assignor's Interest
Dec 1, 1994
From: KOLZE, PAIGE A.
To: QUICKLOGIC CORPORATION
Reel/Frame 007264/0106 →
Assignment of Assignor's Interest
Dec 1, 1994
From: LULLA, MUKESH T.; COX, WILLIAM D.
To: QUICKLOGIC CORPORATION
Reel/Frame 007262/0866 →
Change of Name
May 19, 1995
From: PEER RESEARCH, INC.
To: QUICKLOGIC CORPORATION
Reel/Frame 007516/0737 →
Security Agreement
Oct 19, 1995
From: QUICKLOGIC CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 007696/0480 →
Release of Security Agreement
Jul 1, 1996
From: QUICK LOGIC CORPORATION
To: SILICON VALLEY BANK
Reel/Frame 008018/0367 →
Release of Security Interest
May 7, 2026
From: HERITAGE BANK OF COMMERCE
To: QUICKLOGIC CORPORATION
Reel/Frame 075567/0964 →