Methods of varying read threshold voltage in nonvolatile memory

1. A method of managing a flash memory array comprising:

at a first time, mapping a plurality of memory states of a memory cell to a first voltage threshold window, wherein individual ones of the plurality of memory states are mapped to voltage sub-ranges of the first voltage threshold window; and

at a second time, mapping the plurality of memory states of the memory cell to a second voltage threshold window, wherein individual ones of the plurality of memory states are mapped to voltage sub-ranges of the second voltage threshold window, the second voltage threshold window being wider than the first voltage threshold window so that at least one memory state is mapped into different sub-ranges in the first and second voltage threshold windows.

2. The method of claim 1 further comprising reading the memory cell by using a one of the mappings to determine a specific one of the sub-ranges of the first or second threshold windows in which a first voltage read from such memory cell belongs so as to determine the state of the memory cell.

3. The method of claim 2 further comprising providing results of the reading to a soft-input soft-output decoder that uses the results of the reading as a soft-input to calculate a soft-output according to an encoding scheme.

4. The method of claim 3 , wherein the memory cell is read using the mapping to the first voltage threshold window, the method further comprising:

reading the memory cell by using the mappings to the wider second voltage window to determine a specific one of the voltage sub-ranges of the wider second voltage threshold window in which a second voltage read from the memory cell belongs so as to determine the state of the memory cell, wherein changing from using the mapping to the first voltage threshold window to using the mapping to the second voltage threshold window is in response to information obtained by the soft-input soft-output decoder.

5. The method of claim 1 wherein changing from using the mapping to the first voltage threshold window to using the mapping to the wider second voltage window is in response to a portion of the flash memory array that contains the memory cell being erased more than a predetermined number of times.

6. The method of claim 1 wherein the flash memory array is in a removable memory card that includes a memory controller and an interface for connecting to a host.

7. The method of claim 1 wherein a voltage sub-range of the second threshold voltage window corresponding to a memory state has different upper and lower limits than a voltage sub-range of the first threshold voltage window corresponding to the memory state.

8. A method of reading data from a flash memory array comprising:

reading first data bits from the memory array by comparing threshold voltages of a plurality of memory cells to first predetermined voltages for discriminating between different programmed memory states;

decoding the first data bits in an ECC decoder; and

subsequently reading second data bits from the plurality of memory cells by comparing threshold voltages of the memory cells to second predetermined voltages for discriminating between different programmed memory states and that differs from the first predetermined voltages so that a particular threshold voltage of the first bits results in a different state than the particular threshold voltage of the second bits, the second predetermined voltages determined from the decoding of the first data bits performed in the ECC decoder.

9. The method of claim 8 wherein the ECC decoder is a soft-input soft-output decoder.

10. The method of claim 8 wherein the first predetermined voltages include a first discrimination voltage that discriminate between a first programmed memory state and a second programmed memory state.

11. The method of claim 10 wherein the second predetermined voltages include a second discrimination voltage that differs from the first discrimination voltage and that discriminates between the first programmed memory state and the second programmed memory state, the second discrimination voltage determined from ECC corrections of data in the first programmed memory state and the second programmed memory state.

12. The method of claim 11 wherein the second discrimination voltage is selected to balance the number of corrections by the ECC decoder from the first programmed memory state to the second programmed memory state with the number of corrections by the ECC decoder from the second programmed memory state to the first programmed memory state.

13. The method of claim 8 wherein the second predetermined voltages include a higher voltage than any one of the first predetermined voltages.

14. The method of claim 8 further comprising programming the first data bits to the memory array using a first plurality of target voltages and subsequently adjusting the first plurality of target voltages and then programming a plurality of second data bits to the memory array using the adjusted target voltages.

15. A method of managing a flash memory array that includes memory cells that are programmed to various threshold voltages, comprising:

reading a memory cell by identifying the cell's threshold voltage as being within one of a plurality of first threshold voltage ranges that individually correspond to memory states and additionally resolving within ones of the first threshold voltage ranges to provide an output;

performing ECC correction on the output of the memory cell using a soft-input soft-output decoder;

subsequently erasing and programming the memory cell; and

subsequently reading the memory cell by identifying the cell's threshold voltage as being within one of a plurality of second threshold voltage ranges that individually correspond to the memory states, the one of the plurality of second threshold voltage ranges having a limit for a particular memory state that differs from a one of the plurality of first threshold voltage range's, limit of the same particular memory state, and such one of the plurality of second threshold voltage ranges defined according to the ECC correction performed by the soft-input soft-output decoder.

16. The method of claim 15 wherein the limit of the one of the plurality of second threshold voltage ranges is selected to balance corrections of data in cells having threshold voltages within second threshold voltage ranges on either side of the limit of the one of the plurality of second threshold voltage ranges.

17. The method of claim 15 wherein the limit of the one of the plurality of second threshold voltage ranges is higher than the limit of the one of the first threshold voltage ranges.

18. The method of claim 15 wherein individual ones of the second threshold voltage ranges are wider than individual ones of the first threshold voltage ranges.

19. The method of claim 15 wherein an individual one of the plurality of second threshold voltage ranges corresponding to a memory state extends higher than the one of the plurality of first threshold voltage ranges that corresponds to the memory state.

20. The method of claim 19 wherein the individual voltage range is wider than the one of the plurality of first threshold voltage ranges that corresponds to the memory state.

21. A method of managing a flash memory array comprising:

in a first mode, programming a plurality of memory cells to a first plurality of target voltages, individual ones of the first plurality of target voltages corresponding to memory states;

in the first mode, reading the plurality of memory cells by comparing threshold voltages of the plurality of memory cells with a first plurality of discrimination voltages to determine memory states of individual cells;

subsequently, in a second mode, programming the plurality of memory cells to a second plurality of target voltages that differs from the first plurality of target voltages, individual ones of the second plurality of target voltages corresponding to the memory states; and

in the second mode, reading the plurality of memory cells by comparing threshold voltages of the plurality of memory cells with a second plurality of discrimination voltages, which differs from the first plurality of discrimination voltages, to determine memory states of individual cells.

22. The method of claim 21 wherein an individual one of the second plurality of target voltages corresponding to a particular memory state is greater than an individual one of the first plurality of target voltages corresponding to the particular memory state.

23. The method of claim 21 wherein the second plurality of discrimination voltages are individually offset from the first plurality of discrimination voltages.

24. The method of claim 21 wherein the second plurality of discrimination voltages extend over a greater voltage range than the first plurality of discrimination voltages.