Delay locked loop for an FPGA architecture
View Patent ↗A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
1. A delay lock loop for an FPGA architecture comprising:
an external clock I/O pad;
an internal clock node;
a clock tree having an input and an output, the input of the clock tree coupled to the external clock I/O pad, the internal clock node;
a flip-flop having a clock input coupled to the output of the clock tree, a data input, and a data output;
a reference delay line having an input and an output, the input programmably coupled to the external clock I/O pad and the internal clock node;
a feedback delay line having an input and an output the input programmably coupled to the data output of the flip-flop and the output of the clock tree;
a first divide-by-two circuit having an input coupled to the output of the reference delay line and an output;
a first matching delay line having an input coupled to the output of the reference delay line and an output;
a feedback delay line having an input and an output;
a second divide-by-two circuit having an input coupled to the output of the feedback delay line and an output;
a second matching delay line having an input coupled to the output of the feedback delay line and an output;
a phase detector having first input, a second input, and a plurality of outputs, the first input programmably coupled to one of the output of the first divide-by-two circuit and the first matching delay line, the second input programmably coupled to one of the output of the second divide-by-two circuit and the second matching delay line;
control logic coupled to the plurality of outputs of the phase detector;
a programmable delay line having a reference clock input programmably coupled to one of the external clock I/O pad and the internal clock node, a plurality of data inputs, and an output, the plurality of data inputs coupled to the plurality of outputs of said control logic circuit to receive data to program a delay in the programmable delay line, and an output programmably coupled to one of the input of the clock tree;
a first I/O pad programmably coupled to the data output of the flip-flop; and
a second I/O pad programmably coupled to the clock input of the flip flop and the input to the feedback delay line.
2. The delay lock loop of claim 1 , further comprising:
a first inverter programmably coupled to the input of the reference delay line;
a second inverter programmably coupled to the input of the feedback delay line;
a third inverter programmably coupled to the data input and data output of the flip-flop and the first and second I/O pads.
3. The delay lock loop of claim 1 , further comprising:
a first buffer directly coupled to the external clock I/O pad;
a second buffer directly coupled to the first I/O pad; and
a third buffer directly coupled to the second I/O pad.
4. The delay lock loop of claim 1 wherein the phase detector has three outputs.
5. The delay lock loop of claim 1 , further comprising a clock doubler having an input programmably coupled to the external clock I/O pad, the internal clock node, and the output of the programmable delay line and an output programmably coupled to the input of the clock tree.
6. The delay lock loop of claim 5 configured to perform a 50% duty cycle adjustment.