Method to form selective strained Si using lateral epitaxy
Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.
1. A method of fabricating a semiconductor device comprising:
providing a semiconductor substrate prepared with at least one trench having upper and lower portions;
forming a stress layer in a lower portion of the trench, wherein the stress layer comprises a planar top surface in the lower portion, wherein the stress layer in the trench corresponds to a stressor region; and
forming a semiconductor overlayer in the upper portion of the trench on the planar top surface of the stress layer, wherein the overlayer forms or substantially forms laterally from sides of the semiconductor substrate in upper portion of the trench, wherein the overlayer comprises a planar top surface which is coplanar with a top surface of the substrate.
2. The method of claim 1 wherein the substrate comprises silicon.
3. The method of claim 2 wherein the stress layer comprises an insulating material.
4. The method of claim 2 wherein fanning the overlayer comprises lateral epitaxy.
5. The method of claim 2 wherein the overlayer comprises Si, C doped Si, or SiGe.
6. The method of claim 1 wherein the substrate comprises a (110), (100) or (111) oriented substrate.
7. The method of claim 6 wherein the stress layer comprises an insulating material.
8. The method of claim 6 wherein forming the overlayer comprises lateral epitaxy.
9. The method of claim 8 wherein the overlayer comprises Si, C doped Si, or SiGe.
10. The method of claim 1 wherein forming the overlayer comprises lateral epitaxy, the overlayer comprises a top surface which is coplanar with the substrate.
11. The method of claim 1 wherein the stress layer comprises an insulating material.
12. The method of claim 1 wherein the stress layer comprises silicon nitride or silicon oxide.
13. The method of claim 1 wherein forming the stress layer in the lower portion comprises:
forming a stress inducing layer;
polishing the substrate to form a planar surface with the stress inducing layer and surface of the substrate; and
recessing the stress inducing layer to form the top surface of the stress layer below the surface of the substrate.
14. The method of claim 13 wherein:
forming the overlayer comprises lateral epitaxy; and
the overlayer comprises Si, C doped Si, or SiGe.
15. The method of claim 13 wherein recessing comprises a selective etch back process.
16. The method of claim 15 wherein forming the overlayer comprises lateral epitaxy.
17. The method of claim 1 wherein the stressor region is located below a channel region of a transistor, the stressor region comprises a first stress.
18. The method of claim 17 wherein the first stress comprises tensile stress and the transistor comprises a p-type transistor.
19. The method of claim 17 wherein the first stress comprises compressive stress and the transistor comprises a n-type transistor.
20. A semiconductor device comprising:
a semiconductor substrate having a trench with upper and lower portions;
a stress layer disposed in a lower portion of the trench, wherein the stress layer comprises a planar top surface in the lower portion of the trench; and
a lateral epitaxial overlayer disposed in the upper portion of the trench on the planar top surface of the stress layer, wherein the overlayer comprises a semiconductor material.
21. The semiconductor device of claim 20 wherein the substrate comprises silicon.
22. The semiconductor device of claim 21 wherein the stress layer comprises an insulating material.
23. The semiconductor device of claim 21 wherein the overlayer comprises Si, C doped Si, or SiGe.
24. The semiconductor device of claim 21 wherein the substrate comprises a (110), (100) or (111) oriented substrate.
25. The semiconductor device of claim 24 wherein the stress layer comprises an insulating material.
26. The semiconductor device of claim 24 wherein the overlayer comprises Si, C doped Si, or SiGe.
27. The semiconductor device of claim 20 wherein the overlayer comprises Si, C doped Si, or SiGe, the overlayer comprises a top surface which is coplanar with the substrate.
28. The semiconductor device of claim 20 wherein the stress layer comprises an insulating material.
29. The semiconductor device of claim 20 wherein the stress layer comprises silicon nitride or silicon oxide.
30. The semiconductor device of claim 20 wherein the stress layer in the trench corresponds to a stressor region, the stressor region is located below a channel region of a transistor, and the stressor region comprises a first stress.
31. The semiconductor device of claim 30 wherein the first stress comprises tensile stress and the transistor comprises a p-type transistor.
32. The semiconductor device of claim 30 wherein the first stress comprises compressive stress and the transistor comprises a n-type transistor.