Reduction of sheet resistance of phosphorus implanted poly-silicon
View Patent ↗There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.
1. In an MOS transistor structure, the structure having a gate region, drain region and source region, a method for reducing the sheet resistance of the gate region, the method comprising:
depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region;
implanting amorphizing species at a first predetermined dose into the intrinsic amorphous silicon in the gate region; and
implanting phosphorus species into the gate region at a second predetermined dose.
2. The method as recited in claim 1 , wherein the predetermined temperature is in the range of about 530° C. to about 550° C.
3. The method as recited in claim 1 , wherein the amorphizing species are sufficiently heavy to amorphize silicon.
4. The method as recited in claim 1 , wherein the poly-silicon sheet resistance is adjusted to be in the range of about 18 ohms/square to about 30 ohms/square.
5. The method as recited in claim 1 , wherein the predetermined temperature is in the range of about 535° C. to about 545° C.
6. The method as recited in claim 1 , wherein the predetermined temperature is about 540° C.
7. The method as recited in claim 1 , wherein the first predetermined dose of amorphizing species is in the range of about 1×10 15 cm −2 to about 3×10 15 cm −2 .
8. The method as recited in claim 1 , wherein the second predetermined dose of phosphorus is in the range of about 1×10 14 cm −2 to about 1.6×10 16 cm −2 .
9. The method as recited in claim 1 , wherein the second predetermined dose of phosphorus is about 3.0×10 15 cm −2 .
10. The method as recited in claim 3 , wherein the amorphizing species includes argon, and silicon.
11. A method of forming a MOS integrated circuit comprising:
forming a gate oxide on a substrate;
depositing amorphous silicon on the gate oxide at a predetermined temperature;
amorphizing the amorphous silicon with an Ar+ implant at a predetermined dose;
implanting phosphorus another predetermined dose into the amorphous silicon; and
patterning the amorphous silicon to define a gate region.