Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
View Patent ↗A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
1. A wiring structure of a semiconductor device comprising:
a wiring layer having an upper surface and a lower surface;
an upper plug formed in a first insulating layer above the upper surface of the wiring layer;
a lower plug formed in a second insulating layer below the lower surface of the wiring layer and opposite to the upper plug with the wiring layer interposed; and
at least one cap layer interposed between the wiring layer and any one of the upper plug and the lower plug and positioned below any one of a plane defined by a substantial portion of the upper surface and a plane defined by a substantial portion of the lower surface, respectively,
wherein sizes of grains in a first region of the wiring layer between the upper plug and the lower plug are substantially equal to sizes of grains in a second region laterally adjacent to the first region between the first insulating layer and the second insulating layer.
2. The wiring structure according to claim 1 , wherein the wiring layer has a substantially continuous distribution of grains from the first region to the second region.
3. The wiring structure according to claim 2 , wherein no void is formed between the first region and the second region.
4. The wiring structure according to claim 1 , wherein a surface orientation of the grains in the first region of the wiring layer is substantially equal to a surface orientation of the grains in the second region of the wiring layer.
5. The wiring structure according to claim 4 , wherein no void is formed between the first region and the second region.
6. The wiring structure according to claim 5 , wherein a continuous surface orientation exists from the first region to the second region.
7. The wiring structure according to claim 1 , wherein a distance between a center of a contact surface between the upper plug and the wiring layer and a center of a contact surface between the lower plug and the wiring layer is about ⅔ or more of the diameter of each of the upper plug and the lower plug.
8. The wiring structure according to claim 1 , wherein a distance between a upper surface of the lower plug and the plane defined by the substantial portion of the lower surface is 0.2 μm or less.
9. The wiring structure according to claim 1 , wherein a distance between a upper surface of the lower plug and the plane defined by the substantial portion of the lower surface is about ⅓ or less of the diameter of each of upper plug and lower plug.
10. The wiring structure according to claim 1 , wherein the wiring layer, the upper plug and the lower plug are made of the same material.
11. The wiring structure according to claim 1 , wherein a thermal expansion coefficient of a material of the wiring layer and a thermal expansion coefficient of at least one of the upper plug and the lower plug are substantially equal.
12. The wiring structure according to claim 1 , wherein the at least one cap layer has a thickness excluding a thickness in the range from 10 nm to 80 nm.
13. The wiring structure according to claim 1 , wherein the at least one cap layer has a thickness of 10 nm or less.
14. The wiring structure according to claim 1 , wherein the at least one cap layer has a thickness of 80 nm or more.
15. The wiring structure according to claim 1 , wherein the at least one cap layer is formed of a first cap layer formed on the wiring layer upper surface below the upper plug and a second cap layer different from the first cap layer formed on the wiring layer upper surface below the first insulating layer.
16. The wiring structure according to claim 1 , wherein the at least one cap layer is formed of a first cap layer formed continuously on the wiring layer upper surface below the upper plug and the first insulating layer and a second cap layer different from the first cap layer formed on the first cap layer below the upper plug.
17. The wiring structure according to claim 1 , wherein the at least one cap layer is a continuous layer formed on the wiring layer upper surface below the upper plug and below the first insulating layer.
18. The wiring structure according to claim 1 , wherein the at least one cap layer comprises:
a first cap layer interposed between the wiring layer and the upper plug and positioned below the plane defined by the substantial portion of the upper surface; and
a second cap layer interposed between the wiring layer and the lower plug and positioned below the plane defined by the substantial portion of the lower surface.
19. The wiring structure according to claim 18 , wherein no void is formed between the first region and the second region.
20. The wiring structure according to claim 18 , wherein a surface orientation of the grains in the first region of the wiring layer is substantially equal to a surface orientation of the grains in the second region of the wiring layer.
21. The wiring structure according to claim 20 , wherein no void is formed between the first region and the second region.
22. The wiring structure according to claim 20 , wherein a continuous surface orientation exists from the first region to the second region.
23. The wiring structure according to claim 18 , wherein the distance between a center of a contact surface between the upper plug and the wiring layer and a center of a contact surface between the lower plug and the wiring layer is about ⅔ or more of the diameter of each of the upper plug and the lower plug.
24. The wiring structure according to claim 18 , wherein the distance between a center of a contact surface between the lower plug and the plane defined by the substantial portion of the lower surface is 0.2 μm or less.
25. The wiring structure according to claim 18 , wherein a distance between a upper surface of the lower plug and the plane defined by the substantial portion of the lower surface is about ⅓ or less of the diameter of each of upper plug and lower plug.
26. The wiring structure according to claim 18 , wherein the wiring layer, the upper plug and the lower plug are made of the same material.
27. The wiring structure according to claim 18 , wherein a thermal expansion coefficient of a material of the wiring layer and a thermal expansion coefficient of at least one of the upper plug and the lower plug are substantially equal.
28. The wiring structure according to claim 18 , wherein the second cap layer has a thickness excluding a thickness in the range from 10 nm to 80 nm.
29. The wiring structure according to claim 18 , wherein the second cap layer has a thickness of 10 nm or less.
30. The wiring structure according to claim 18 , wherein the second cap layer has a thickness of 80 nm or more.
31. The wiring structure according to claim 18 , wherein the second cap layer is a continuous layer formed below the lower surface of the wiring layer and above the lower plug and the second insulating layer.
32. The wiring structure according to claim 18 , wherein the wiring layer has a substantially continuous distribution of grains from the first region to the second region.