Nonvolatile semiconductor memory having voltage adjusting circuit
View Patent ↗Nonvolatile evaluation memory cells are programmed to be a plurality of different values in advance, respectively. An internal voltage generating circuit can change the value of an internal voltage according to adjusting signals. To make the internal voltage close to its expected value, a voltage adjusting circuit outputs adjusting signals in accordance with cell currents that flow through the evaluation memory cells, respectively, in a read operation on the evaluation memory cells. As a result, the interval voltage that is shifted from its expected value due to variations in manufacturing conditions can automatically be set to the expected value by using the adjusting signals. Since an internal circuit operates on a correct internal voltage, operation margins can be increased. The yield of a nonvolatile semiconductor memory can thus be increased.
1. A nonvolatile semiconductor memory comprising:
nonvolatile normal memory cells;
a normal word line connected to said normal memory cells;
nonvolatile evaluation memory cells programmed in advance to be set to a plurality of different values, respectively;
an internal voltage generating circuit which generates, for use in an internal circuit, an internal voltage which is changeable by an adjusting signal; and
a voltage adjusting circuit which outputs said adjusting signal in accordance with cell currents in a read operation on said evaluation memory cells, to make a value of the internal voltage close to an expected value, the cell currents flowing through the respective evaluation memory cells, wherein;
said internal voltage generating circuit generates, as said internal voltage, a control voltage to be supplied to said normal word line.
2. The nonvolatile semiconductor memory according to claim 1 , further comprising:
an evaluation word line connected to said evaluation memory cells, wherein:
said internal voltage generating circuit generates said control voltage to be supplied to said evaluation word line; and
said voltage adjusting circuit outputs said adjusting signal in accordance with said cell currents so as to make said control voltage close to the expected value.
3. The nonvolatile semiconductor memory according to claim 2 , further comprising
a cell array in which said normal memory cells are formed, wherein
said evaluation memory cells are formed in said cell array together with said normal memory cells.
4. The nonvolatile semiconductor memory according to claim 2 , further comprising
a test circuit which activates said evaluation word line during a test mode and prohibits activation of said evaluation word line during a normal operation mode.
5. The nonvolatile semiconductor memory according to claim 1 , further comprising
a nonvolatile reference memory cell programmed in advance to be set to a predetermined threshold voltage and receiving a constant voltage at a control gate thereof, wherein:
said voltage adjusting circuit comprises differential sense amplifiers formed in correspondence with said respective evaluation memory cells and each having a pair of differential inputs; and
each of said differential sense amplifiers is connected to a data output node of a corresponding evaluation memory cell at one of said differential inputs, and connected to a data output node of said reference memory cell at the other of said differential inputs, to output bit values of said adjusting signal from the output nodes.
6. The nonvolatile semiconductor memory according to claim 5 , further comprising
a nonvolatile memory circuit which stores the bit values of said adjusting signal output from said differential amplifiers.