Data throttling circuit and method for a spacewire application
View Patent ↗A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit 0 is transmitted for half the time and bit 1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit 0 and one bit 1.
1. A Data Throttling circuit for a SpaceWire application comprising:
bit generation logic having an output for providing data and an input for receiving a throttle control signal; and
a flip-flop having an input coupled to the output of the bit generation logic, a clock input for receiving a clock signal, and an output for providing output data,
wherein the bit generation logic and the flip-flop are coupled together in an open-loop configuration, and
wherein, in an open throttle condition output data is able to change on every clock cycle, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
2. The Data Throttling circuit as in claim 1 , wherein the clock signal has a rate in excess of 10 Mhz.
3. The Data Throttling circuit as in claim 1 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.
4. A Data Throttling circuit for a SpaceWire application comprising:
a first bit generation logic circuit having an output for providing data and an input for receiving a throttle control signal;
a second bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
a first flip-flop having an input coupled to the output of the first bit generation logic circuit, a clock input for receiving a clock signal, and an output for providing output data;
a second flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
a first multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a control node for receiving a first control signal, and an output for providing output data; and
a second multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a control node for receiving a second control signal, and an output for providing output data,
wherein the first bit generation logic circuit and the first flip-flop are coupled together in an open-loop configuration, the second bit generation logic circuit and the second flip-flop are coupled together in an open-loop configuration, and
wherein, in an open throttle condition output data is able to change on every clock cycle, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
5. The Data Throttling circuit as in claim 4 , wherein the clock signal has a rate in excess of 10 Mhz.
6. The Data Throttling circuit as in claim 4 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.
7. A Data Throttling circuit for a SpaceWire application comprising:
a first bit generation logic circuit having an output for providing data and an input for receiving a throttle control signal;
a second bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
a third bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
a fourth bit generation logic circuit having an output for providing data and an input for receiving the throttle control signal;
a first flip-flop having an input coupled to the output of the first bit generation logic circuit, a clock input for receiving a clock signal, and an output for providing output data;
a second flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
a third flip-flop having an input coupled to the output of the third bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
a fourth flip-flop having an input coupled to the output of the second bit generation logic circuit, a clock input for receiving the clock signal, and an output for providing output data;
a first multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a first control signal, and an output for providing output data; and
a second multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a second control signal, and an output for providing output data,
a third multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a third control signal, and an output for providing output data; and
a fourth multiplexer having a first input coupled to the output of the first flip-flop, a second input coupled to the output of the second flip-flop, a third input coupled to the output of the third flip-flop, a fourth input coupled to the output of the fourth flip-flop, a control node for receiving a fourth control signal, and an output for providing output data,
wherein the first bit generation logic circuit and the first flip-flop are coupled together in an open-loop configuration, the second bit generation logic circuit and the second flip-flop are coupled together in an open-loop configuration, the third bit generation logic circuit and the third flip-flop are coupled together in an open-loop configuration, the fourth bit generation logic circuit and the fourth flip-flop are coupled together in an open-loop configuration, and
wherein, in an open throttle condition output data is able to change on every clock cycle, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
8. The Data Throttling circuit as in claim 7 , wherein the clock signal has a rate in excess of 10 Mhz.
9. The Data Throttling circuit as in claim 7 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.
10. A Data Throttling method for a SpaceWire application comprising:
providing output data by an open-loop system; and
providing a clock signal,
wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
11. The Data Throttling circuit as in claim 10 , wherein the clock signal has a rate in excess of 10 Mhz.
12. The Data Throttling circuit as in claim 10 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.
13. A Data Throttling method for a SpaceWire application comprising:
providing an output data pair by an open-loop system; and
providing a clock signal,
wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
14. The Data Throttling method as in claim 13 , wherein the clock signal has a rate in excess of 10 Mhz.
15. The Data Throttling method as in claim 13 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.
16. The Data Throttling method as in claim 13 , wherein, for an even throttling rate output data bit pairs are provided corresponding to either a first data input bit or a second data input bit.
17. A Data Throttling method as in claim 13 , wherein, for an odd throttling rate output data bit pairs corresponding are provided corresponding to a first data input bit, a second data input bit, or a split pair including both the first data input bit and the second data input bit.
18. A Data Throttling method for a SpaceWire application comprising:
providing a four-bit output data word by an open-loop system; and
providing a clock signal,
wherein, in an open throttle condition output data is able to change on every clock cycle of the clock signal, and, in a closed throttle condition current output data is held until the closed throttle condition is released.
19. The Data Throttling method as in claim 18 , wherein the clock signal has a rate in excess of 10 Mhz.
20. The Data Throttling method as in claim 18 , wherein the effective data transmission rate of the output data in a closed throttle condition is 10 Mhz.