IP Library Granted Patent US 7,605,457
Granted Patent B2
US 7,605,457 · App. 11/636,155 · Granted Oct 20, 2009

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,605,457
App. No.
11/636,155
Filed
Dec 7, 2006
Granted
Oct 20, 2009
Kind
B2
Art Unit
2811
USPC
257/686
Abstract

The present invention provides a semiconductor device that includes: stacked semiconductor chips, each semiconductor chip including a semiconductor substrate and a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed on side faces thereof; first metal layers that are provided in center portions of inner side faces of the concavities; and second metal layers that are provided in the concavities and are connected to the first metal layers formed on each semiconductor chip. The present invention also provides a method of manufacturing the semiconductor device.

Claims (22)

1. A semiconductor device comprising:

a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces of the semiconductor substrate and has concavities formed through and on side faces of the first insulating layer, and first metal layers that are provided in center portions of inner side faces of the concavities; and

second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips.

2. The semiconductor device as claimed in claim 1 , wherein the first insulating layer is provided on an upper face of the semiconductor substrate.

3. The semiconductor device as claimed in claim 2 , wherein:

the first metal layers are provided on an upper face of the first insulating layer; and

the semiconductor device further comprises a second insulating layer that is formed on upper faces of the first metal layers.

4. The semiconductor device as claimed in claim 1 , wherein:

the at least one of the semiconductor chips includes pad electrodes that are provided on the semiconductor substrate;

the first insulating layer has openings that are formed over the pad electrodes; and

the first metal layers are also provided on an upper face of the first insulating layer, and are connected to the pad electrodes through the openings.

5. A semiconductor device comprising

a package that has a built-in semiconductor device mounted therein, the built-in semiconductor device being the semiconductor device as claimed in any of claim 1 .

6. The semiconductor device as claimed in claim 5 , wherein:

the package has a substrate; and

the built-in semiconductor device is face-down mounted on the substrate.

7. The semiconductor device as claimed in claim 5 , wherein:

the package has a lead frame; and

the built-in semiconductor device is sealed with resin.

8. A semiconductor device comprising:

a plurality of stacked semiconductor chips, at least one of the semiconductor chips including a semiconductor substrate, a first insulating layer that is provided on side faces and an upper face of the semiconductor substrate, first metal layers that are provided on side faces and an upper face of the first insulating layer, and a second insulating layer that is provided on upper faces of the first metal layers and side faces of the first insulating layer and the first insulating layer has concavities formed through and on the side faces thereof, and

second metal layers that are provided in the concavities and are connected to the first metal layers formed on the at least one of the semiconductor chips, the second metal layers being connected to the first metal layers through the concavities.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036044/0122 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2007
From: HOSHINO, MASATAKA; KASAI, JUNICHI; MEGURO, KOUICHI; FUKUYAMA, RYOTA; SHINMA, YASUHIRO; TAYA, KOJI; ONODERA, MASANORI; MASUDA, NAOMI
To: SPANSION LLC.
Reel/Frame 019007/0883 →