Memory modules with error detection and correction
View Patent ↗A memory module having error detection and correction mechanisms. The memory module includes a plurality of memory devices arranged in an array and a buffer device connected to the memory devices. The buffer device includes a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of the input signals and transmitting the stored copy of the input signals as an output signal. A buffer device for a memory module. A method of operating a memory module. A memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.
1. A memory module, comprising:
a plurality of memory devices arranged in an array; and
a buffer device connected to the memory devices, the buffer device including a register module for synchronizing and buffering a plurality of input signals to the memory devices, an error detection module for detecting errors of the input signals, and a transmission memory for storing a copy of at least a portion of the input signals and transmitting the stored copy as an output signal;
the transmission memory including a plurality of parallel-in/serial-out registers arranged in a pipeline.
2. The memory module of claim 1 wherein the transmission memory further includes a decoder for addressing the plurality of parallel-in/serial-out registers.
3. The memory module of claim 1 wherein the pipeline is synchronized with a clock signal.
4. The memory module of claim 1 wherein the pipeline is asynchronous without a clock signal.
5. The memory module of claim 1 wherein the buffer device further includes an input terminal for receiving a system parity signal and an output terminal for sending an error signal.
6. The memory module of claim 5 wherein the output terminals from the error detection module and the transmission memory are tied using a device functional as a logic OR before being applied to the output terminal for sending the error signal.
7. The memory module of claim 1 wherein the memory devices are selected from a group consisting of DRAM, SDRAM, SRAM, DDR1, DDR2, DDR3, RLDRAM, FCRAM, Flash memory, and Synchronous Flash memory.
8. A computing device incorporating the memory module of claim 1 and further including a motherboard carrying a processor and a memory controller.
9. A memory module, comprising:
a plurality of memory devices arranged in an array; and
a buffer device connected to the memory devices,
the buffer device including:
a register module for synchronizing and buffering a plurality of input signals to the memory devices;
an error detection module for detecting errors of the input signals; and
a transmission memory for storing a copy of at least a portion of the input signals and transmitting the stored copy as an output signal, wherein the transmission memory has a capacity of N number of words each having M bytes, wherein M corresponds at least in part to a size of the input signals and N corresponds to a number of copies of the input signals to be stored in the transmission memory.
10. A memory module, comprising:
a plurality of memory devices arranged in an array; and
a buffer device connected to the memory devices,
the buffer device including:
a register module for synchronizing and buffering a plurality of input signals to the memory devices;
an error detection module for detecting errors of the input signals; and
a transmission memory for storing a copy of at least a portion of the input signals and transmitting the stored copy as an output signal, wherein the error detection module calculates a register parity bit based on the input signals, compares the calculated register parity bit to a system parity bit, and declares an error if the register parity bit does not match the system parity bit.
11. A buffer device for a memory module having a plurality of memory devices, comprising:
a plurality of input terminals for receiving a plurality of input signals;
a register module for buffering the plurality of received input signals to the memory devices;
an error detection module for detecting errors of the input signals; and
a transmission memory for storing at least one copy of the input signals and transmitting the stored at least one copy of the input signals as an output signal to an external device;
the transmission memory includes a plurality of parallel-in/serial-out registers arranged in a pipeline.
12. The buffer device of claim 11 wherein the pipeline is synchronized with a clock signal.
13. The buffer device of claim 11 wherein the pipeline is asynchronous without a clock signal.
14. The buffer device of claim 11 wherein the buffer device further includes an input terminal for receiving a system parity signal and an output terminal for sending an error signal.
15. The buffer device of claim 14 wherein the output terminals from the error detection module and the transmission memory are tied using a device functional as a logic OR before being applied to the output terminal for sending the error signal.
16. The memory module of claim 11 wherein the memory devices are selected from a group consisting of DRAM, SDRAM, SRAM, DDR1, DDR2, DDR3, RLDRAM, FCRAM, Flash memory, and Synchronous Flash memory.
17. A computing device incorporating the buffer device of claim 11 and further including a motherboard carrying a processor and a memory controller.
18. A buffer device for a memory module having a plurality of memory devices, comprising:
a plurality of input terminals for receiving a plurality of input signals;
a register module for buffering the plurality of received input signals to the memory devices;
an error detection module for detecting errors of the input signals; and
a transmission memory for storing at least one copy of the input signals and transmitting the stored at least one copy of the input signals as an output signal to an external device; and the transmission memory has a capacity of N number of words each having M bytes, wherein M corresponds at least in part to a size of the input signals and N corresponds to a number of copies of the input signals to be stored in the transmission memory.
19. A buffer device for a memory module having a plurality of memory devices comprising:
a plurality of input terminals for receiving a plurality of input signals;
a register module for buffering the plurality of received input signals to the memory devices;
an error detection module for detecting errors of the input signals; and
a transmission memory for storing at least one copy of the input signals and transmitting the stored at least one copy of the input signals as an output signal to an external device; and
the error detection module calculates a register parity bit based on the input signals, compares the calculated register parity bit to a system parity bit, and declares an error if the register parity bit does not match the system parity bit.
20. A method of operating a memory module in a computing device, comprising:
calculating a system parity bit based on a set of input signals before sending the set of input signals from a memory controller to the memory module;
transmitting the set of input signals along with the calculated system parity bit to the memory module;
storing a copy of the input signals in a transmission memory and calculating a register parity bit based on the set of input signals received by the memory module;
comparing the register parity bit to the system parity bit; and
declaring an error if the register parity bit does not match the system parity bit; and
wherein the transmission memory includes a plurality of registers arranged in a pipeline, and wherein the method further includes storing additional copies of the input signals in a first-in/first-out fashion.
21. The method of claim 20 wherein the set of input signals includes at least one of an address signal and a command signal.
22. The method of claim 20 , further comprising transmitting the stored copy of the input signal to the memory controller.
23. An apparatus for use with an external memory having at least one memory device, comprising:
a plurality of input terminals for receiving a plurality of input signals;
a register module buffering the plurality of received input signals to the at least one memory device;
an error detection module for detecting errors of the input signals; and
a second memory including a plurality of registers arranged in a pipeline for storing a plurality of copies of the input signals and communicating the stored copies of the input signals as an output signal to an external device.
24. The apparatus of claim 23 , wherein the plurality of registers are configured for storing the plurality of copies of the input signals in a first-in/first-out fashion.
25. The apparatus of claim 23 , wherein the second memory has a capacity of N number of words each having M bytes, wherein M corresponds at least in part to a size of the input signals and N corresponds to a number of copies of the input signals to be stored in the transmission memory.
26. The apparatus of claim 23 , wherein the second memory includes a plurality of parallel-in/serial-out registers arranged in a pipeline.
27. The apparatus of claim 23 , wherein the error detection module calculates a register parity bit based on the input signals, compares the calculated register parity bit to a system parity bit, and declares an error if the register parity bit does not match the system parity bit.
28. A method of operating a memory, comprising:
calculating a system parity information based on a set of input signals before sending the set of input signals from a memory controller to the memory;
communicating the set of input signals with the calculated system parity to the memory;
storing copies of the input signals in a second memory having a plurality of storage elements arranged in a pipeline in a first-in first-out manner, and calculating register parity information based on the set of input signals received by the memory;
comparing the register parity information to the system parity information; and
declaring an error if the register parity information does not match the system parity information.
29. The method in claim 28 , wherein the plurality of copies of the input signals are sequential versions of the input signals received at different sequential times.
30. The method in claim 28 , wherein the storage elements comprise storage registers, the register parity information comprises a register parity bit, and the system parity information comprises a system parity bit.