Stacked semiconductor device
View Patent ↗A stacked semiconductor device includes an interposer substrate having external power supply terminals, and semiconductor chips stacked on the interposer substrate. A power supply wiring arranged in the semiconductor chip located in the bottom layer is connected to the external power supply terminal via a bump electrode, the power supply wiring arranged in the semiconductor chip located in the top layer is connected to the external power supply terminal via a bonding wire, and the power supply wirings each arranged in adjacent semiconductor chips are mutually connected via the through electrode. Such a loop structure can solve a problem such that the higher the semiconductor chip, the larger its voltage drop.
1. A stacked semiconductor device in which a plurality of semiconductor chips including at least first and second semiconductor chips are stacked, comprising:
an external power supply terminal;
a first connector that electrically connects a power supply wiring arranged in the first semiconductor chip and the external power supply terminal;
a second connector outside said semiconductor chips that electrically connects a power supply wiring arranged in the second semiconductor chip and the external power supply terminal; and
a third connector that mutually electrically connects the power supply wirings each provided in adjacent semiconductor chips.
2. The stacked semiconductor device as claimed in claim 1 , wherein the third connector includes a through electrode arranged in the plurality of semiconductor chips.
3. The stacked semiconductor device as claimed in claim 1 , wherein
the plurality of semiconductor chips further include a third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip, and
a power supply wiring of the third semiconductor chip is electrically connected to the power supply wirings of the first and the second semiconductor chips by the third connector, and is electrically connected in a bypassing manner to the external power supply terminal by a fourth connector different from the third connector.
4. The stacked semiconductor device as claimed in claim 1 , further comprising an interposer substrate on which the external power supply terminal is arranged, wherein the plurality of semiconductor chips are stacked on the interposer substrate.
5. The stacked semiconductor device as claimed in claim 4 , wherein the first semiconductor chip is a semiconductor chip nearest to the interposer substrate.
6. The stacked semiconductor device as claimed in claim 5 , wherein the first connector includes a bump electrode that electrically connects the power supply wiring arranged in the first semiconductor chip and a power supply wiring arranged in the interposer substrate.
7. The stacked semiconductor device as claimed in claim 4 , wherein the second semiconductor chip is a semiconductor chip farthest from the interposer substrate.
8. The stacked semiconductor device as claimed in claim 7 , wherein the second connector includes a bypass conductor that electrically connects the power supply wiring arranged in the second semiconductor chip and a power supply wiring arranged in the interposer substrate.
9. The stacked semiconductor device as claimed in claim 8 , wherein a plurality of the bypass conductors are arranged in parallel.
10. The stacked semiconductor device as claimed in claim 8 , wherein the bypass conductor is a bonding wire.
11. The stacked semiconductor device as claimed in claim 7 , further comprising a cap substrate arranged opposite, seen from the second semiconductor chip, to the interposer substrate, wherein the second connector electrically connects the external power supply terminal and the power supply wiring that is arranged in the second semiconductor chip, via the power supply wiring arranged in the cap substrate.
12. The stacked semiconductor device as claimed in claim 11 , further comprising an underfill material that is arranged between the interposer substrate and the cap substrate, and covers the plurality of semiconductor chips.
13. The stacked semiconductor device as claimed in claim 4 , wherein
the plurality of semiconductor chips further include a third semiconductor chip arranged between the first semiconductor chip and the second semiconductor chip, and
a power supply wiring of the third semiconductor chip is electrically connected to the power supply wirings of the first and the second semiconductor chips by the third connector, and is electrically connected in a bypassing manner to the external power supply terminal by a fourth connector different from the third connector.
14. The stacked semiconductor device as claimed in claim 13 , further comprising an intermediate interposer substrate arranged between the first semiconductor chip and the second semiconductor chip, wherein
the power supply wiring arranged in the third semiconductor chip and a power supply wiring arranged on the intermediate interposer substrate are electrically connected by a bump electrode, and
the fourth connector includes a bypass conductor that electrically connects the power supply wiring arranged on the interposer substrate and the power supply wiring arranged on the intermediate interposer substrate.
15. A stacked semiconductor device, comprising:
a plurality of stacked semiconductor chips; and
a power supply wiring that supplies a power supply potential to the plurality of semiconductor chips, wherein
the power supply wiring has a loop structure that includes a portion that goes through a through electrode arranged in the plurality of semiconductor chips, and a portion that goes through at least one bypass conductor.
16. The stacked semiconductor device as claimed in claim 15 , further comprising an interposer substrate on which the plurality of semiconductor chips are mounted, wherein one end of the at least one bypass conductor is connected to the interposer substrate, and the other end of the at least one bypass conductor is connected to one of the plurality of semiconductor chips that is arranged in a top layer.
17. The stacked semiconductor device as claimed in claim 15 , wherein
the plurality of semiconductor chips include at least a first semiconductor chip group and a second semiconductor chip group,
the at least one bypass conductor includes first and second bypass conductors, and
the loop structure of the power supply wiring includes a first loop structure including a portion that goes through a through electrode arranged in the first semiconductor chip group and a portion that goes through the first bypass conductor; and a second loop structure including a portion that goes through a through electrode arranged in the second semiconductor chip group and a portion that goes through the first and the second bypass conductors.
18. The stacked semiconductor device as claimed in claim 17 , further comprising an intermediate interposer substrate arranged between the first semiconductor chip group and the second semiconductor chip group, wherein
one end of the first bypass conductor is connected to the interposer substrate and the other end of the first bypass conductor is connected to the intermediate interposer substrate, and
one end of the second bypass conductor is connected to the interposer substrate and the other end of the second bypass conductor is connected directly or indirectly to a semiconductor chip that is arranged in a top layer and included in the second semiconductor chip group.