Methods and systems for high write performance in multi-bit flash memory devices
View Patent ↗Methods and circuits for performing high speed write (programming) operations in a dual-bit flash memory array. The method includes, for example, erasing a first and second bit of each cell in the array to a first state, programming the first bit of each cell in the array to a second state, and subsequently programming the second bit of one or more cells in the array to one of the first and second state according to the user's data, resulting in fast write (programming) of those second bits. In addition, the circuit includes, for example, a core cell array having dual-bit flash memory cells configured into a plurality of array portions. The circuit further includes a control circuit configured to selectively block erase one of the array portions, wherein in a first phase of the block erase both first and second bit locations of each dual-bit flash memory cell in the one array portion have sufficient charge removed therefrom to achieve a first state. The control circuit is further configured to, in a second phase of the block erase, supply charge to the first bit location of each dual-bit flash memory cell of the one array portion to enable subsequently fast-write of user's data to the second bit location.
1. A method of partitioning a multi-bit flash memory array into a fast write portion and a normal write portion, comprising:
identifying an array portion of dual-bit flash memory cells for fast write operations thereto; and
performing a fast write enabling erase operation on the identified fast write array portion prior to a write operation thereto, wherein the fast write enabling erase operation differs from an erase operation to be performed on another array portion comprising a normal write array portion of memory cells that is not identified for fast write operations thereto.
2. The method of claim 1 , wherein performing the fast write enabling erase operation comprises:
erasing both first and second bit locations for each cell in the identified fast write array portion; and
supplying charge to the first bit location for each cell in the identified fast write array portion, wherein the supplied charge to the first bit locations is unrelated to user data, thereby providing for subsequent fast write operations to the second bit locations of each cell therein.
3. The method of claim 2 , wherein erasing both first and second bit locations comprises removing sufficient charge from both bit locations so as to be read as each bit in the identified fast write array portion residing at a first state.
4. The method of claim 3 , wherein supplying charge to the first bit location comprises supplying sufficient charge thereto so as to achieve a subsequent write operation to the second bit location of each cell in the identified fast write array portion less than a predetermined time period.
5. The method of claim 3 , wherein supplying charge to the first bit location comprises supplying sufficient charge thereto so as to be read as each first bit location in the identified fast write array portion residing at a second state.
6. The method of claim 1 , wherein identifying the fast write array portion comprises:
loading a command register with a value indicative of a fast write mode at a location within the command register associated with the identified fast write array portion; or
setting the flash memory array in a “fast write mode”, where all following commands will be considered relating to fast-write portions.
7. The method of claim 6 , further comprising performing an erase of the multi-bit flash memory array, wherein performing the erase comprises:
identifying a portion of the memory array to be erased;
evaluating a mode of the command register at a location therein associated with the identified array portion to be erased; and
performing either the fast write erase operation or a normal erase operation that differs from the fast write erase operation on the identified array portion based on the evaluation.
8. The method of claim 1 , wherein the array portion comprises a plurality of memory blocks that are not physically continuous with respect to one another.