Row selector occupying a reduced device area for semiconductor memory devices
View Patent ↗A memory device having a plurality of memory cells grouped in at least two memory sectors is disclosed. A first decoding circuit operable to receive address codes of the plurality of memory cells and to generate a plurality of decoding and selecting signals in response to the address codes. A plurality of second decoding circuits are coupled to the first decoding circuit and operable to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals. A voltage shifting circuit is operable to generate a shift in the voltage of the plurality of decoding and selecting signals for generating a plurality of shifted voltage decoding and selecting signals and to provide the shifted decoding and selecting signals to the plurality of second decoding signals for generating the drive signals.
1. A memory device comprising:
a plurality of memory cells, said memory cells being grouped in at least two memory sectors,
a plurality of memory cell address signal lines respectively coupled to the memory cells;
a first decoding circuit coupled to an address bus to receive address codes of the memory cells from the address bus and, in response thereto, to assert a plurality of decoding and selecting signals common to said at least two memory sectors;
a plurality of second decoding circuits respectively coupled to said at least two memory sectors, each second decoding circuit also being coupled to the first decoding circuit to receive said plurality of decoding and selecting signals and to generate driving signals for driving said memory cell address signal lines depending on said decoding and selecting signals; and
a plurality of voltage boosting blocks coupled to said first decoding circuit and to said plurality of second decoding circuits for receiving said plurality of decoding and selecting signals and shifting the plurality of decoding and selecting signals in voltage to a shifted-voltage level to generate respective shifted decoding and selecting signals common to the at least two memory sectors, and to provide the shifted decoding and selecting signals to the plurality of second decoding circuits to generate the driving signals.
2. The memory device according to claim 1 , wherein each one of the second decoding circuits comprises:
a plurality of driving circuits to generate said driving signals for driving said memory cell address signal lines, each driving circuit being coupled to at least one corresponding memory cell address signal line of a respective one of the at least two memory sectors;
a plurality of control signal generator blocks to generate control signals for said driving circuits in response to at least one first subset of said shifted decoding and selecting signals; and
a plurality of supply voltage signal generator circuits to generate supply voltage signals for said driving circuits in response to at least one second subset of said shifted decoding and selecting signals, said supply voltage signals forming supply voltages.
3. The memory device according to claim 2 , wherein each one of the at least two memory sectors comprises at least one packet of the memory cell address signal lines wherein each of the supply voltage signal generator circuits is coupled to a corresponding one of the memory cell address signal lines of the at least one packet, and the at least one packet of said memory cell address signal lines is coupled to a corresponding one of the plurality of control signal generator blocks.
4. The memory device according to claim 1 , wherein said first decoding circuit asserts at least two sector selection signals, each one corresponding to a respective memory sector of the at least two memory sectors in response to the address codes, and wherein said voltage boosting blocks further include sector voltage boosting blocks to generate shifted sector selection signals, said shifted sector selection signals being provided to the plurality of second decoding circuits in combination with said shifted decoding and selecting signals common to the at least two memory sectors.
5. The memory device according to claim 4 , further comprising a plurality of control signal generator blocks, wherein each control signal generator block includes a first NAND logic gate, said first NAND logic gate being connected to an even number of first inverter logic circuits to provide a corresponding control signal in response to a first combination of said shifted decoding and selecting signals with the corresponding shifted sector selection signal.
6. The memory device according to claim 4 , wherein each of a plurality of supply voltage signal generator circuits includes a second NAND logic gate and a second inverter logic circuit, said second NAND logic gate being to provide a corresponding supply voltage signal in response to a second combination of said shifted decoding and selecting signals with the corresponding shifted sector selection signal.
7. The memory device according to claim 1 , wherein said voltage boosting blocks include:
a voltage-shifter block having a first and a second transistor of a first conductivity type, and a third and a fourth transistor of a second conductivity type connected according to a latch structure, wherein the third and the fourth transistors are structured to receive a biasing voltage having a value corresponding to the shifted voltage level; and
inverter connected to the voltage-shifter block.
8. The memory device according to claim 7 , wherein said voltage boosting blocks include one of a plurality of voltage-shifter blocks for each of the shifted decoding and selecting signal common to the at least two memory sectors.
9. The memory device according to claim 1 , wherein said memory cells are electrically programmable, and said driving signals are adapted to bias the memory cell address signal lines to a voltage suitable to allow for programming of the cells.
10. The memory device according to claim 1 , wherein said memory cells include flash memory cells.
11. A method of operation of a memory device, comprising the steps of:
grouping a plurality of memory cells in at least two memory sectors;
associating with each of the memory cells a respective one of a plurality of memory cell address signal lines;
receiving an address code;
performing a first decoding of the address code of the memory cells and, in response thereto, asserting a plurality of decoding and selecting signals common to said at least two memory sectors; and
performing a second decoding, for each one of the at least two memory sectors, for generating driving signals for said memory cell address signal lines depending on said decoding and selecting signals; shifting a voltage of said decoding and selecting signals for generating respective shifted decoding and selecting signals common to the at least two memory sectors; and
generating the driving signals using the shifted decoding and selecting signals.
12. The method of claim 11 wherein performing the first decoding, further includes:
generating at least two sector selection signals in response to receiving the address code wherein each of the at least two sector selection signals corresponds to a respective one of the at least two memory sectors.
13. The method of claim 12 , further includes: generating shifted sector selection signals by voltage shifting the at least two sector selection signals.
14. The method of claim 13 wherein performing the second decoding, further includes:
generating control signals for a plurality of driving circuits in response to at least one first subset of the shifted decoding and selecting signals; and generating supply voltage signals for the plurality of driving circuits in response to at least one second subset of the shifted decoding and selecting signals wherein the supply voltage signals form supply voltages.
15. The method of claim 14 wherein generating the control signals, further includes:
communicatively coupling a first NAND logic gate to an even number of first inverter logic circuits and providing a corresponding one of the control signals in response to a first combination of the shifted decoding and selecting signals with a corresponding one of the shifted sector selection signals.
16. The method of claim 15 wherein generating the supply voltage signals, further includes:
communicatively coupling a second NAND logic gate to a second inverter logic circuit and providing a corresponding one of the supply voltage signals in response to a second combination of the shifted decoding and selecting signals with the corresponding one of the shifted sector selection signals.
17. A memory device comprising:
a plurality of memory cells grouped in at least two memory sectors wherein each of the at least two memory sectors have a memory cell arrangement allowing access to each memory cell via respective memory cell address signal lines;
a first decoding circuit coupled to an address bus to receive address codes of the plurality of memory cells from the address bus and to generate a plurality of decoding and selecting signals in response to the address codes;
a plurality of second decoding circuits coupled to the first decoding circuit to receive said plurality of decoding and selecting signals and to generate driving signals for the memory cell address signal lines based at least in part on the plurality of decoding and selecting signals; and
a voltage boosting block coupled to said first decoding circuit and to said plurality of second decoding circuits to receive said plurality of decoding and selecting signals and to generate a shift in voltage of the plurality of decoding and selecting signals and provide shifted decoding and selecting signals to the plurality of second decoding circuits for generating the drive signals.
18. The memory device of claim 17 wherein said first decoding circuit generates at least two sector selection signals in response to the address codes, wherein each of the at least two sector selection signals corresponds to a respective one of the at least two memory sectors.
19. The memory device of claim 18 wherein the voltage boosting blocks further shift a voltage of the at least two sector selection signals to generate shifted sector selection signals, the shifted sector selection signals being provided to the plurality of second decoding circuits in combination with the shifted decoding and selecting signals.
20. The memory device of claim 19 wherein each of the plurality of second decoding circuits, further comprises:
a plurality of driving circuits to generate the driving signals for the memory cell address signal lines;
a plurality of control signal generator blocks to generate control signals for the plurality of driving circuits in response to at least one of the shifted decoding and selecting signals; and
a plurality of supply voltage signal generator circuits to generate supply voltage signals for the plurality of driving circuits in response to at least one of the shifted decoding and selecting signals.