Radiation tolerant SRAM bit
View Patent ↗In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
1. In an integrated circuit, a radiation tolerant static random access memory device comprising:
a first inverter having an input and an output;
a second inverter having an input and an output, said output of said first inverter coupled to said input of said second inverter and said output of said second inverter coupled to said input of said first inverter;
a write transistor coupled to said output of one of said first inverter and said second inverter and having a gate coupled to a source of write-control signals,
a resistor coupled between said first and second inverter;
a pass transistor having a gate coupled to one of said first inverter output and said second inverter output wherein;
an RC time constant of the static random access memory device exceeds a selected recovery time of the static random access memory device.
2. The radiation tolerant static random access memory device of claim 1 wherein the resistor has a resistance of about 4M ohms.
3. In an integrated circuit, a method of producing a radiation tolerant static random access memory device comprising:
providing a first inverter having an input and an output;
coupling a second inverter having an input and an output to said output of said first inverter to said input of said second inverter and coupling said output of said second inverter to said input of said first inverter;
coupling a resistor between said first and second inverter; and
coupling a pass transistor gate to one of said first inverter output and said second inverter output; and
coupling a write transistor to an output of one of said first inverter and said second inverter and coupling a gate to a source of write-control signals,
wherein an RC time constant of the static random access memory device exceeds a selected recovery time of the static random access memory device.
4. The method of claim 3 wherein coupling a resistor between said first and second inverter comprises coupling a resistor that has a resistance of about 4M ohms.