Dedicated input/output first in/first out module for a field programmable gate array

1. A field programmable gate array architecture having a plurality of input/output pads comprising:

a plurality of logic clusters;

a plurality of input/output clusters;

a plurality of input/output buffers;

a plurality of dedicated input/output first-in/first-out memory blocks, said dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of said plurality of input/output pads;

an input/output block controller programmably coupled to said plurality of dedicated input/output first-in/first-out memory blocks, wherein said input/output block controller comprises a dedicated FIFO flag logic block coupled to said plurality of input/output clusters; and

a routing interconnect architecture programmably coupling said logic clusters, input/output buffers and said input/output clusters,

wherein said dedicated input/output first-in/first-out memory blocks are programmably coupled between said input/output buffers and said input/output clusters.

2. The field programmable gate array architecture of claim 1 , further comprising a plurality of registers coupled to said first-in/first-out memory.

3. The field programmable gate array architecture of claim 2 , wherein said plurality of registers comprises an input register, an output register, and an enable register.

4. The field programmable gate array architecture of claim 1 , wherein said dedicated FIFO flag logic block is configured to generate full, empty, almost-full, and almost-empty flags.

5. The field programmable gate array architecture of claim 1 , further comprising a plurality of random access memory clusters.