Method of generating test patterns to efficiently screen inline resistance delay defects in complex asics
View Patent ↗A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.
1. A pattern generator apparatus configured to generate scan based patterns for a plurality of transition delay faults, said pattern generator apparatus comprising:
means for maintaining a fault universe;
means for targeting at least one of the plurality of said transition delay faults and generating a pattern based on said at least one of the plurality of said transition delay faults;
means for fault simulating the pattern to determine if said at least one of the plurality of said transition delay faults is detected;
means for removing the detected at least one of the plurality of said transition delay faults as well as a companion fault of said detected transition delay fault from said fault universe even though said companion fault has not been detected if said at least one of the plurality of said transition delay faults is detected.
2. The pattern generator apparatus as recited in claim 1 , wherein the means for removing said companion fault comprises means for removing a fault on a node which is the same as the detected transition delay fault but having the opposite transition.
3. The pattern generator apparatus as recited in claim 1 , wherein the means for maintaining said fault universe comprises means for maintaining a list of said plurality of transition delay faults.
4. The pattern generator apparatus as recited in claim 1 , wherein the means for targeting at least one of the plurality of said transition delay faults and fault simulating the pattern comprises means for generating the pattern based on a slow-to-rise (STR) transition fault, and wherein the means for removing the detected as well as the companion fault comprises if the slow-to-rise (STR) transition fault is detected, comprises means for removing the slow-to-rise (STR) transition fault as well as its companion slow-to-fall (STF) transition fault from said fault universe.
5. The pattern generator apparatus as recited in claim 1 , wherein the means for targeting at least one of the plurality of said transition delay faults and fault simulating the pattern comprises means for generating the pattern based on a slow-to-fall (STF) transition fault, and wherein the means for removing the detected as well as the companion fault comprises if the slow-to-fall (STF) transition fault is detected, comprises means for removing the slow-to-fall (STF) transition fault as well as its companion slow-to-rise (STR) transition fault from said fault universe.
6. The pattern generator apparatus as recited in claim 1 , wherein the means for targeting at least one of the plurality of said transition delay faults and fault simulating the pattern comprises means for generating the pattern based on a slow-to-rise (STR) transition fault, and wherein the means for removing the detected as well as the companion fault comprises if the slow-to-rise (STR) transition fault is detected, comprises means for removing the slow-to-rise (STR) transition fault as well as its companion slow-to-fall (STF) transition fault from said fault universe, and wherein the means for targeting at least one of the plurality of said transition delay faults and fault simulating the pattern comprises means for generating the pattern based on a slow-to-fall (STF) transition fault, and wherein the means for removing the detected as well as the companion fault comprises means for removing the slow-to-fall (STF) transition fault as well as its companion slow-to-rise (STR) transition fault from said fault universe if the slow-to-fall (STF) transition fault is detected.
7. The pattern generator apparatus as recited in claim 1 , further comprising means for continuing until all of said plurality of transition delay faults are either detected or deemed untestable.