Non-volatile memory with cache page copy
View Patent ↗A non-volatile memory and methods includes cached page copying using a minimum number of data latches for each memory cell. Multi-bit data is read in parallel from each memory cell of a group associated with a first word line. The read data is organized into multiple data-groups for shuttling out of the memory group-by-group according to a predetermined order for data-processing. Modified data are returned for updating the respective data group. The predetermined order is such that as more of the data groups are processed and available for programming, more of the higher programmed states are decodable. An adaptive full-sequence programming is performed concurrently with the processing. The programming copies the read data to another group of memory cells associated with a second word line, typically in a different erase block and preferably compensated for perturbative effects due to a word line adjacent the first word line.
1. A non-volatile memory, comprising:
an array of memory cells, wherein individual memory cells are each programmable to one of multiple memory states;
a multi-bit code having multiple code bits for encoding each of the multiple memory states;
a predetermined bit order of the code bits such that as more of the higher order code bits are available, more of the higher programmed states are decodable;
a set of latches for latching the multi-bit data of each memory cell of a memory cell group, the set of latches having capacity just for the multiple code bits plus an additional bit;
a controller in response to a request for copying a group of data from a first memory cell group to a second memory cell group, wherein said controller performing operations that comprise:
reading from memory cells of the first memory cell group to determine the memory states programmed therein;
encoding each read memory state as multi-bit data with the multi-bit code;
latching the multi-bit data of every memory cell of the first memory cell group;
grouping the latched data into as many data groups as the number of code bits, each data group collecting a same code bit from every memory cell of the first memory cell group;
processing the data groups, data group by data group according to the predetermined code bit order, by outputting the bits of each data group to a controller for data-processing and returning any modified bits to update each data group;
if any data group has been processed, simultaneously with any additional data group processing, programming individual memory cells of the second memory cell group up to a highest memory state decodable by available code bits from the processed data groups; and
repeating the processing and the programming until all code bits of the multi-bit code are available to complete said programming.
2. The non-volatile memory as in claim 1 , wherein the set of latches has capacity just for the multiple code bits plus an additional bit.
3. The non-volatile memory as in claim 1 , wherein the reading including correcting for any perturbative effects due to memory cells of a neighboring word line.
4. The non-volatile memory as in claim 1 , wherein the multi-bit code contains two bits.
5. The non-volatile memory as in claim 1 , wherein the multi-code contains three bits.
6. The non-volatile memory as in claim 1 , wherein the multi-code contains four bits.
7. The non-volatile memory as in claim 1 , wherein the array of memory cells is organized into a plurality of erasable blocks of memory cells, and the first memory cell group and the second memory cell group belong to different erasable blocks.
8. The non-volatile memory as in claim 1 , wherein the array of memory cells is organized into a plurality of erasable blocks of memory cells, and the first memory cell group and the second memory cell group belong to the same erasable block.
9. The non-volatile memory as in claim 1 , wherein the non-volatile memory is a flash EEPROM.
10. The non-volatile memory as in claim 1 , wherein the non-volatile memory has a NAND structure.
11. The non-volatile memory as in claim 1 , wherein the non-volatile memory is on a removable memory card.
12. The non-volatile memory as in claim 1 , wherein the non-volatile memory has memory cells with a floating gate structure.
13. The non-volatile memory as in claim 1 , wherein the non-volatile memory comprises memory cells with a dielectric layer structure.
14. The non-volatile memory as in claim 2 , wherein said reading including correcting for any perturbative effects due to memory cells of a neighboring word line.
15. The non-volatile memory as in claim 2 , wherein the multi-bit code contains two bits.
16. The non-volatile memory as in claim 2 , wherein the multi-code contains three bits.
17. The non-volatile memory as in claim 2 , wherein the multi-code contains four bits.
18. The non-volatile memory as in claim 2 , wherein the array of memory cells is organized into a plurality of erasable blocks of memory cells, and the first memory cell group and the second memory cell group belong to different erasable blocks.
19. The non-volatile memory as in claim 2 , wherein the array of memory cells is organized into a plurality of erasable blocks of memory cells, and the first memory cell group and the second memory cell group belong to the same erasable block.
20. The non-volatile memory as in claim 2 , wherein the non-volatile memory is a flash EEPROM.
21. The non-volatile memory as in claim 2 , wherein the non-volatile memory has a NAND structure.
22. The non-volatile memory as in claim 2 , wherein the non-volatile memory is on a removable memory card.
23. The non-volatile memory as in claim 2 , wherein the non-volatile memory comprises memory cells with a floating gate structure.
24. The method as in claim 2 , wherein the non-volatile memory comprises memory cells with a dielectric layer structure.
25. A non-volatile memory, comprising:
an array of memory cells, wherein individual memory cells are each programmable to one of multiple memory states;
a multi-bit code having multiple code bits for encoding each of the multiple memory states;
a predetermined bit order of the code bits such that as more of the higher order code bits are available, more of the higher programmed states are decodable;
a set of latches for latching the multi-bit data of each memory cell of a memory cell group, the set of latches having capacity just for the multiple code bits plus an additional bit;
means for reading from memory cells of the first memory cell group to determine the memory states programmed therein;
means for encoding each read memory state as multi-bit data with the multi-bit code;
means for latching the multi-bit data of every memory cell of the first memory cell group;
means for grouping the latched data into as many data groups as the number of code bits, each data group collecting a same code bit from every memory cell of the first memory cell group;
means for processing the data groups, data group by data group according to the predetermined code bit order, by outputting the bits of each data group to a controller for data-processing and returning any modified bits to update each data group;
if any data group has been processed, simultaneously with any additional data group processing, means for programming individual memory cells of the second memory cell group up to a highest memory state decodable by available code bits from the processed data groups; and
means for repeating the processing and the programming until all code bits of the multi-bit code are available to complete said programming.
26. The non-volatile memory as in claim 25 , wherein the set of latches has capacity just for the multiple code bits plus an additional bit.