Method of making reliable wafer level chip scale package semiconductor devices
View Patent ↗The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.
1. A method of making a wafer level chip scale package comprising the steps of:
forming a semiconductor wafer containing a plurality of circuits in a plurality of layers at each of a plurality of different chip areas, wherein the semiconductor wafer includes for each of the plurality of different chip areas a plurality of conductive bond pads connected to conductive wires;
creating a compressive stress within a passivation layer that is applied directly on the plurality of conductive bond pads and the conductive wires, the compressive stress being created using an insulating material for the passivation layer, which insulating material is applied in a highly compressive manner relative to the plurality of layers, thereby causing a completed passivation layer to maintain the compressive stress therein, such that the compressive stress will substantially minimize cracks within the passivation layer during subsequent processing;
removing contact areas from portions of the passivation layer to expose certain ones of the plurality of conductive bond pads, wherein the compressive stress within remaining portions of the passivation layer is maintained after the step of removing contact areas is completed;
applying an underbump material over each of the exposed conductive bond pads;
placing a conductive bump over the underbump material associated with each of the certain ones of the plurality of conductive bond pads and attaching it to the underbump material using a thermal flow cycle; and
dicing the wafer to obtain a plurality of bumped die, wherein the compressive stress of the completed passivation layer in an area surrounding each of the plurality of conductive bond pads is maintained after the step of dicing the wafer is completed.
2. The method according to claim 1 wherein the step of applying includes the steps of depositing an underbump material layer, photolithographically defining an area for the underbump material and removing excess of the underbump material layer to define the underbump material; and further comprising the steps of:
mounting one of the bumped die onto a surface of a printed circuit board, thereby establishing electrical connection between a conductive pad on the printed circuit board to a corresponding conductive bump on the bumped die, the step of mounting including reflowing each of the conductive bumps and thereby establish electrical contact between each of the electrical contacts and associated ones of the conductive bond pads, and wherein during reflowing the integrity of the passivation layer is maintained due to the usage of the insulating material applied in the highly compressive manner relative to the plurality of layers.
3. The method according to claim 2 further including the steps of:
mounting at least one other die onto the surface after the step of mounting the one bumped die, wherein the step of mounting the at least one other die causes a further thermal cycle on the passivation layer of the one bumped die, and the integrity of the passivation layer is maintained during the further thermal cycle due to the usage of the insulating material applied in the highly compressive manner relative to the plurality of layers.
4. The method according to claim 3 wherein the step of mounting is repeated multiple times, thereby causing additional thermal cycles, and wherein the integrity of the passivation layer is maintained during the additional thermal cycles due to the usage of the insulating material applied in the highly compressive manner relative to the plurality of layers.
5. The method according to claim 1 wherein the insulating material applied in the highly compressive manner relative to the plurality of layers includes a silicon nitride layer with a stress value that is greater than 5E9 dynes/cm2.
6. The method according to claim 5 wherein the insulating material that forms the completed passivation layer is formed as a plurality of passivation layers, including a silicon nitride layer and a silicon dioxide layer, wherein at least a top one of the plurality of passivation layers is applied in the highly compressive manner relative to the plurality of layers to maintain compressive stress in the completed passivation layer that will substantially minimize cracks therein during subsequent processing.
7. The method according to claim 6 wherein the completed passivation layer has a thickness between 15-25 KA.
8. The method according to claim 7 wherein the completed passivation layer has a thickness between 17-20 KA.
9. The method according to claim 1 wherein the completed passivation layer has a thickness between 10-25 KA.
10. The method according to claim 1 wherein the completed passivation layer has a thickness between 17-20 KA.
11. The method according to claim 10 wherein the insulating material is silicon nitride.
12. The method according to claim 11 wherein the insulating material that forms the completed passivation layer is formed as a plurality of passivation layers, including a silicon nitride layer and a silicon dioxide layer.
13. The method according to claim 9 wherein the insulating material is silicon nitride.
14. The method according to claim 13 wherein the insulating material that forms the completed passivation layer is formed as a plurality of passivation layers, including an silicon nitride layer and an silicon dioxide layer.
15. The method according to claim 1 , further including a step of forming a protective film over the completed passivation layer, the protective film having a coefficient of thermal expansion that is at least 5 times greater than a coefficient of thermal expansion of the complete passivation layer and a Young's Modulus smaller than that of the completed passivation layer.
16. The method according to claim 1 wherein the completed passivation layer includes a nitride, or a combination of nitride and oxide, and the protective layer includes a polyimide.
17. The method according to claim 1 wherein the step of creating the compressive stress includes forming a plurality of passivation layers as the completed passivation layer, and wherein a top one of the plurality of passivation layers is made with an insulating material that is applied in a compressive manner with a greatest stress value as compared to other ones of the plurality of passivation layers to maintain the highly compressive stress that will substantially minimize cracks therein during subsequent processing.
18. The method according to claim 17 wherein the top one of the plurality of passivation layers is a silicon nitride layer with a stress value that is greater than 5E9 dynes/cm2.
19. The method according to claim 18 wherein the completed passivation layer has a thickness between 17-20 KA.
20. The method according to claim 1 wherein the step of creating the compressive stress includes forming a plurality of passivation layers as the completed passivation layer, and wherein each of the plurality of passivation layers is made with an insulating material that is applied in a highly compressive manner relative to the plurality of layers to maintain compressive stress that will substantially minimize cracks therein during subsequent processing.
21. The method according to claim 20 wherein at least one of the plurality of passivation layers is a silicon nitride layer with a stress value that is greater than 5E9 dynes/cm2.
22. The method according to claim 21 wherein the completed passivation layer has a thickness between 17-20 KA.