Method to form upward pointing p-i-n diodes having large and uniform current

1. A method for forming a vertically oriented p-i-n diode, the method comprising:

forming a first rail-shaped conductor above a substrate;

forming the p-i-n diode by:

(a) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductor;

(b) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type region of deposited semiconductor material, wherein the middle intrinsic or lightly doped region of deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy;

(c) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a pillar;

(d) forming a top heavily doped n-type region of deposited semiconductor material by doping with arsenic;

forming a silicide-forming metal region in contact with the top heavily doped n-type region of the p-i-n diode;

forming a silicide, germanide, or silicide-germanide by reacting the silicide-forming metal region with the top heavily doped n-type region of the p-i-n diode; and

annealing to crystallize the deposited semiconductor material, where some portion of the deposited semiconductor material was amorphous as deposited and is in contact with the silicide, germanide, or silicide-germanide before the annealing step.

2. The method of claim 1 wherein the silicide is titanium silicide, titanium germanide, titanium silicide-germanide, cobalt silicide, cobalt germanide, or cobalt silicide-germanide.

3. The method of claim 1 wherein the top heavily doped n-type region is doped in situ.

4. The method of claim 1 wherein the top heavily doped n-type region is doped by doping the top of the middle intrinsic or lightly doped region by ion implantation.

5. The method of claim 4 wherein ion implantation to form the top heavily doped n-type region takes place before the patterning and etching step.

6. The method of claim 4 wherein ion implantation to form the top heavily doped n-type region takes place after the patterning and etching step.

7. The method of claim 1 further comprising forming a titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer above and in contact with the top heavily doped n-type region, wherein the silicide, germanide, or silicide-germanide is formed when a portion of the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer reacts with the top heavily doped n-type region.

8. The method of claim 7 wherein the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer is a portion of a top conductor.

9. The method of claim 7 wherein the titanium, cobalt, chromium, tantalum, platinum, niobium, or palladium layer is a portion of a hard mask used to etch the pillar during the patterning and etching step.

10. The method of claim 1 wherein the p-i-n diode is a portion of a memory cell, wherein the memory cell further comprises:

a portion of the first rail-shaped conductor;

a portion of a second rail-shaped conductor above the p-i-n diode, the p-i-n diode disposed between the first rail-shaped conductor and the second rail-shaped conductor.

11. The method of claim 10 wherein the memory cell further comprises a dielectric rupture antifuse, the dielectric rupture antifuse and the p-i-n diode arranged electrically in series between the first conductor and the second conductor.

12. The method of claim 11 wherein the dielectric rupture antifuse comprises HfO 2 , Al 2 O 3 , ZrO 2 , TiO 2 , La 2 O 3 , Ta 2 O 5 , RuO 2 , ZrSiO x , AlSiO x , HfSiO x , HfAlO x , HfSiON, ZrSiAlO x , HfSiAlO x , HfSiAlON, or ZrSiAlON.

13. The method of claim 11 wherein the dielectric rupture antifuse comprises silicon dioxide.

14. The method of claim 10 wherein the memory cell further comprises a resistivity-switching element, the resistivity-switching element and the p-i-n diode arranged electrically in series between the first conductor and the second conductor.

15. The method of claim 14 wherein the resistivity-switching element comprises a binary metal oxide.

16. The method of claim 15 wherein the binary metal oxide is selected from the group consisting of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and Al x N y .

17. The method of claim 14 wherein the resistivity-switching element comprises carbon nanotube fabric.

18. The method of claim 1 wherein the substrate is a monocrystalline silicon wafer.

19. A method for forming a monolithic three dimensional memory array, the method comprising:

a) monolithically forming a first memory level above a substrate by:

i) forming a first plurality of rail-shaped conductors above the substrate;

forming a plurality of p-i-n diodes by:

(a) forming a bottom heavily doped p-type region of deposited semiconductor material above the first rail-shaped conductors;

(b) forming a middle intrinsic or lightly doped region of deposited semiconductor material above the bottom heavily doped p-type semiconductor, wherein the middle intrinsic or lightly doped region of deposited semiconductor material is silicon, germanium, or a silicon-germanium alloy;

(c) patterning and etching the bottom heavily doped p-type region and the middle intrinsic or lightly doped region to form a first plurality of pillars;

(d) forming a top heavily doped n-type region of deposited semiconductor material by doping with arsenic;

ii) forming a silicide-forming metal region in contact with the top heavily doped n-type region of the p-i-n diodes;

iii) forming a silicide, germanide, or silicide-germanide by reacting the silicide-forming metal region with the top heavily doped n-type region of the p-i-n diodes;

iv) annealing to crystallize the deposited semiconductor material, where some portion of the deposited semiconductor material was amorphous as deposited and is in contact with the silicide, germanide, or silicide-germanide before the annealing step; and

v) forming a second plurality of rail-shaped conductors above the middle intrinsic or lightly doped region, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising a portion of one of the first rail-shaped conductors, one of a first plurality of pillars, and a portion of one of the second conductors,

b) monolithically forming a second memory level above the first memory level.

20. The method of claim 19 wherein the second memory level comprises a second plurality of p-i-n diodes, each second p-i-n diode comprising a portion of a second bottom heavily doped n-type region, a portion of a second middle intrinsic or lightly doped region, and a portion of a second top heavily doped p-type region.

21. The method of claim 20 wherein the second conductors are shared by the first memory level and the second memory level.