NAND memory with side-tunneling
View Patent ↗A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer.
1. A NAND flash memory comprising:
a plurality of memory cells connected in series in a first direction to form a NAND string, each memory cell having a floating gate;
a plurality of control gates extending in a second direction that is perpendicular to the first direction, an individual one of the plurality of floating gates coupled to two control gates; and
wherein odd numbered memory cells have a first set of physical properties and even numbered memory cells have a second set of physical properties.
2. The NAND flash memory of claim 1 wherein the first set of physical properties includes a first gate dielectric thickness and the second set of physical parameters includes a second gate dielectric thickness.
3. The NAND flash memory of claim 1 wherein the first set of physical properties includes a first cell threshold voltage and the second set of physical properties includes a second threshold voltage.
4. The NAND flash memory of claim 1 wherein the odd numbered memory cells have a first floating gate to channel coupling ratio and the even numbered memory cells have a second floating gate to channel coupling ratio.
5. The NAND flash memory of claim 1 wherein each of the plurality of floating gates has an inverted-T shape in cross section.
6. The NAND flash memory of claim 1 further comprising a tunnel dielectric layer that separates the individual ones of the plurality of control gates from floating gates.
7. The NAND flash memory of claim 6 further comprising a gate dielectric layer that separates the plurality of floating gates from an underlying substrate.
8. A NAND flash memory array comprising:
a floating gate having a first control gate on a first side and a second control gate on an opposing second side, the first and second control gates separated from the floating gate by a tunnel dielectric, the floating gate separated from an underlying substrate by a gate dielectric layer, the gate dielectric layer including a blocking layer that blocks tunneling of electrons between the substrate and the floating gate.
9. The NAND flash memory array of claim 8 wherein the tunnel dielectric layer is a Silicon dioxide layer.
10. The NAND flash memory array of claim 8 wherein the blocking layer is a Silicon Nitride layer.
11. The NAND flash memory array of claim 8 wherein the first control gate couples to a first neighboring floating gate and the second control gate couples to a second neighboring floating gate.
12. The NAND flash memory of claim 8 wherein the floating gate is formed from a first layer and the first and second neighboring floating gates are formed from a second layer.
13. A NAND string comprising:
a plurality of floating gate memory cells connected in series in a first direction, each of the plurality of floating gate memory cells having a floating gate, odd numbered ones of the plurality of floating gates formed from a first layer, even numbered ones of the plurality of floating gates formed from a second layer;
a plurality of control gates that extend in a second direction that is perpendicular to the first direction, each of the plurality of control gates coupled to two of the plurality of floating gates;
a tunnel dielectric layer that separates one of the plurality of control gates from one of the plurality of floating gates to allow electron tunneling; and
a blocking dielectric layer between the plurality of floating gates and an underlying substrate, the blocking layer blocking electron tunneling.
14. The NAND string of claim 13 wherein individual ones of the plurality of floating gates have an inverted-T shape in cross section.
15. The NAND string of claim 13 further comprising a plurality of word lines extending over the plurality of control gates so that an individual one of the plurality of control gates is electrically connected to an individual one of the plurality of word lines.
16. The NAND string of claim 15 wherein the plurality of word lines connect the plurality of control gates to control gates of other NAND strings.
17. The NAND string of claim 16 wherein shallow trench isolation structures separate the NAND string from the other NAND strings.