IP Library Granted Patent US 7,474,386
Granted Patent B2
US 7,474,386 · App. 11/710,552 · Granted Jan 6, 2009

Wafer flatness evaluation method, wafer flatness evaluation apparatus carrying out the evaluation method, wafer manufacturing method using the evaluation method, wafer quality assurance method using the evaluation method, semiconductor device manufacturing method using the evaluation method and semiconductor device manufacturing method using a wafer evaluated by the evaluation method

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Quick Facts
Patent No.
US 7,474,386
App. No.
11/710,552
Granted
Jan 6, 2009
Kind
B2
Abstract

There is disclosed a wafer flatness evaluation method includes measuring front and rear surface shapes of a wafer. The wafer front surface measured is divided into sites. Then, a flatness calculating method is selected according to a position of the site to be evaluated and flatness in the wafer surface is acquired.

Claims (42)

1. A wafer manufacturing method comprising:

acquiring a wafer from an ingot based on a working process condition set;

measuring front and rear surface shapes of the acquired wafer;

dividing the front surface of the wafer into sites, selecting a flatness calculating method according to a predetermined factor to be evaluated and acquiring flatness in the wafer surface;

determining whether or not the acquired flatness in the wafer surface satisfies a requirement from a budget;

fixing the set working process condition when the flatness in the wafer surface satisfies the requirement from the budget; and

changing the set working process condition when the flatness in the wafer surface does not satisfy the requirement from the budget.

2. The wafer manufacturing method according to claim 1 , wherein the wafer is one of a mirror-surface wafer, epitaxial wafer, anneal wafer and SOI wafer.

3. The wafer manufacturing method according to claim 1 , wherein the predetermined factor is a position of a site.

4. The wafer manufacturing method according to claim 1 , wherein the predetermined factor is the rear surface shape of the wafer in a site.

5. The wafer manufacturing method according to claim 1 , wherein the predetermined factor is a stage shape of a wafer holder lying under a site.

6. A semiconductor device manufacturing method comprising:

extracting a wafer which is being worked after a working process of a semiconductor device and before a lithography process;

measuring front and rear surface shapes of the extracted wafer;

dividing the front surface of the wafer into sites, selecting a flatness calculating method according to a predetermined factor to be evaluated and acquiring flatness in the wafer surface;

determining whether or not the acquired flatness in the wafer surface maintains a value which satisfies a requirement from a budget or maintains a value which causes no problem;

fixing working process conditions of the working process and lithography process when the flatness of the wafer surface maintains the above value; and

changing at least one of the working process conditions of the working process and the lithography process when the flatness of the wafer surface does not maintain the above value.

7. The semiconductor device manufacturing method according to claim 6 , wherein the predetermined factor is a position of a site.

8. The semiconductor device manufacturing method according to claim 6 , wherein the predetermined factor is the rear surface shape of the wafer in a site.

9. The semiconductor device manufacturing method according to claim 6 , wherein the predetermined factor is a stage shape of a wafer holder lying under a site.

10. A semiconductor device manufacturing method comprising:

measuring a thickness variation of a wafer in a free standing state;

deriving local flatness on a reference of a wafer rear surface on the assumption that the rear surface of the wafer is corrected to a flat plane based on the result of the measurement;

deriving a local flatness transfer constant corresponding to magnitude of the local flatness on the reference of the wafer rear surface;

calculating local flatness of the wafer front surface at the time of chucking on a wafer holder based on a value of the flatness transfer constant and the local flatness on the reference of the wafer rear surface;

determining whether or not the wafer is acceptable based on the above calculation; and

manufacturing a semiconductor device by use of the wafer which is determined acceptable based on the above determination.

11. A semiconductor device manufacturing method comprising:

measuring a thickness variation of a wafer in a free standing state;

deriving local flatness on a reference of a rear surface of the wafer on the assumption that the rear surface of the wafer is corrected to a flat plane based on the result of the measurement;

dealing with the local flatness on the reference of the wafer rear surface as a final result when magnitude of the local flatness on the reference of the wafer rear surface does not exceed a preset value and performing a simulation for chucking the wafer on a wafer holder when the magnitude of the local flatness on the reference of the wafer rear surface exceeds the preset value;

calculating local flatness of the wafer front surface at the time of chucking on the wafer holder based on the result of simulation;

determining whether or not the wafer is acceptable based on the above calculation; and

manufacturing a semiconductor device by use of the wafer which is determined acceptable based on the above determination.

12. A semiconductor device manufacturing method comprising:

measuring a thickness variation of a wafer in a free standing state;

deriving local flatness on a reference of a rear surface of the wafer on the assumption that the rear surface of the wafer is corrected to a flat plane based on the result of the measurement;

dealing with the local flatness on the reference of the wafer rear surface as a final result when magnitude of the local flatness on the reference of the wafer rear surface does not exceed a preset value and chucking the wafer on a wafer holder when the magnitude of the local flatness on the reference of the wafer rear surface exceeds the preset value;

calculating local flatness based on the wafer front surface shape in the chucking state;

determining whether or not the wafer is acceptable based on the above calculation; and

manufacturing a semiconductor device by use of the wafer which is determined acceptable based on the above determination.

Assignments (3)
MERGER AND CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058785/0124 →
CHANGE OF NAME Recorded Jan 20, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058785/0197 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 044384/0054 →