Static random access memory cell
View Patent ↗A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node to which a read signal is applied and is configured to generate an output signal that is the complement of an input signal in response to an active read signal. The SRAM cell further includes an access transistor having a first node coupled to the output of the tri-state inverter and having a second node coupled to the digit line. The access transistor is configured to couple the first and second nodes in response to an active access signal applied to its gate.
1. A digital image sensor, comprising:
an active pixel sensor array;
an analog processing circuit coupled to the active pixel sensor array;
an analog-to-digital converter (ADC) circuit coupled to the analog processing circuit;
a control circuit coupled to the active pixel sensor array, the analog processing circuit, and the ADC circuit;
a control register coupled to the control circuit; and
a dual port memory coupled to the analog processing circuit and the control circuit, the dual port memory comprising:
an input bus;
an output bus;
an input/output circuit coupled to the input and output busses and configured to write data received on the input bus during a write operation and provide read data to the output bus during a read operation, the input/output circuit comprising a plurality of amplifier circuits each coupled to one of a plurality of digit lines, each amplifier circuit having a first pair of series coupled tri-state inverters coupled between the input bus and a respective digit line and a second pair of series coupled tri-state inverters coupled between the respective signal digit and the output bus;
control circuitry coupled to the input/output circuit and configured to control the input/output circuits during write and read operations;
a memory array coupled to the input/output circuit, the memory array having a plurality of memory cells, each of the memory cells coupled to one of the plurality of digit lines, each memory cell comprising:
a first inverter having a first input node and a first output node;
a second inverter having a second input node, a second output node, and a control node at which a control signal is applied, the second inverter configured to be disabled in response to an active control signal, the second output node coupled to the first input node and the first output node coupled to the second input node; and
an access switch having a first node coupled to the second output node, having a second node coupled to the digit line, and further having a switch node to which a switch signal is applied, the access switch configured to couple the first and second nodes in response to an active switch signal; and
wherein the control circuitry is operable to generate the control signal and the switch signal, the control circuitry operable to execute a write operation by coupling the active switch signal to the access switch while applying the active control signal to the second inverter, then coupling an inactive switch signal to the access switch while applying an inactive control signal to the second inverter, activating the second inverter.
2. The digital image sensor of claim 1 wherein each amplifier circuit is configured to capture write date coupled to the input bus prior to writing the write data to at least one memory cell coupled to the respective digit line and further configured to capture read data coupled to the respective digit line prior to coupling the read data to the output bus.
3. A dual port memory, comprising:
an input bus;
an output bus;
an input/output circuit coupled to the input and output busses and configured to write data received on the input bus during a write operation and provide read data to the output bus during a read operation, the input/output circuit comprising a plurality of amplifier circuits having a digit node coupled to a respective one of a plurality of digit lines, an input node coupled to the input bus, and an output node coupled to the output bus, each amplifier circuit having a first pair of series coupled tri-state inverters coupled between the input bus and the respective digit line and a second pair of series coupled tri-state inverters coupled between the respective digit line and the output bus;
control circuitry coupled to the input/output circuit and configured to control the input/output circuits during write and read operations; and
a memory array coupled to the input/output circuit, the memory array having a plurality of memory cells, each of the memory cells coupled to one of a plurality of signal lines coupled to the input/output circuit, each memory cell comprising:
a first inverter having a first input node and a first output node;
a second inverter having a second input node, a second output node, and a control node at which a control signal is applied, the second inverter configured to be disabled in response to an active control signal, the second output node coupled to the first input node and the first output node coupled to the second input node; and
an access switch having a first node coupled to the second output node, having a second node coupled to the signal line, and further having a switch node to which a switch signal is applied, the access switch configured to coupled the first and second nodes in response to an active switch signal.
4. The dual port memory of claim 3 wherein the first inverter of a memory cell comprises a complementary metal-oxide-semiconductor (CMOS) inverter coupled between a voltage supply and ground.
5. The dual port memory of claim 3 wherein the second inverter of a memory cell comprises:
first and second p-channel metal-oxide-semiconductor (PMOS) transistors coupled in series between a voltage supply and the first node of the access switch, the first PMOS transistor having a first PMOS gate to which a complementary control signal is applied and the second PMOS transistor having a second PMOS gate coupled to the first output node; and
first and second n-channel metal-oxide-semiconductor (NMOS) transistors coupled in series between the first node of the access switch and ground, the first NMOS transistor having a first NMOS gate to which the control signal is applied and the second NMOS transistor having a second NMOS gate coupled to the first output node.
6. The dual port memory of claim 3 wherein the access switch of a memory cell comprises a n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the switch signal is applied.
7. The dual port memory of claim 3 wherein each amplifier circuit is configured to capture write date coupled to the input bus prior to writing the write data to at least one memory cell coupled to the respective digit line and further configured to capture read data coupled to the respective digit line prior to coupling the read data to the output bus.
8. The dual port memory of claim 3 wherein the control circuitry is operable to generate the control signal and the switch signal, the control circuit operable to execute a write operation by coupling the active switch signal to the access switch while applying the active control signal to the second inverter, then coupling an inactive switch signal to the access switch while applying an inactive control signal to the second inverter, activating the second inverter.