Static random access memory cell
View Patent ↗A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node to which a read signal is applied and is configured to generate an output signal that is the complement of an input signal in response to an active read signal. The SRAM cell further includes an access transistor having a first node coupled to the output of the tri-state inverter and having a second node coupled to the digit line. The access transistor is configured to couple the first and second nodes in response to an active access signal applied to its gate.
1. A memory comprising:
a sense amplifier comprising a first plurality of tri-state inverters configured to couple a digit line to an input bus and a second plurality of tri-state inverters configured to couple the digit line to an output bus; and
a memory cell coupled to the digit line, comprising:
a first inverter having a first supply terminal coupled to a voltage supply and a first ground terminal coupled to ground, and further having a first input and a first output, the first inverter configured to generate a first output signal at the first output that is the complement of a first input signal in response to receiving the first input signal at the first input;
a second inverter having a second supply terminal and a second ground terminal, and further having a second input coupled to the first output and a second output coupled to the first input, the second inverter configured to generate a second output signal at the second output that is the complement of the first output signal in response to a supply voltage coupled to the second supply terminal and ground coupled to the second ground terminal;
a first switch having a first node coupled to the voltage supply and a second node coupled to the second supply terminal and further having a control node to which a first read signal is applied, the first switch configured to couple the first and second nodes in response to an active first read signal;
a second switch having a first node coupled to the second ground terminal and a second node coupled to ground and further having a control node to which a second read signal is applied, the second switch configured to couple the first and second nodes in response to an active second read signal; and
an access transistor having a first node coupled to the second output, a second node coupled to the digit line, and a control node to which an access signal is applied, the access transistor configured to couple the first and second nodes in response to an active access signal.
2. The memory of claim 1 wherein the first switch comprises a p-channel metal-oxide-semiconductor (PMOS) transistor and wherein the second switch comprises a n-channel metal-oxide-semiconductor (NMOS) transistor.
3. The memory of claim 1 wherein the first inverter comprises a complementary metal-oxide-semiconductor (CMOS) inverter.
4. The memory of claim 1 wherein the first switch comprises a p-channel metal-oxide-semiconductor (PMOS) transistor having a gate to which the first read signal is applied.
5. The memory of claim 1 wherein the second switch comprises a n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the second read signal is applied.
6. The memory of claim 1 wherein the access transistor comprises a n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the access signal is applied.
7. The memory of claim 1 wherein the first read signal comprises a signal that is the complement of the second read signal.
8. A memory comprising:
a sense amplifier comprising a first tri-state inverter configured to couple a digit line to an input bus and a second tri-state inverter configured to couple the digit line to an output bus; and
a memory cell, comprising:
a first inverter having a supply terminal coupled to a voltage supply and a first ground terminal coupled to ground, the first inverter having a first input and a first output, the first inverter operable to generate a first output signal;
a second inverter having a second supply terminal and a second ground terminal, the second inverter having a second input coupled to the first output of the first inverter and a second output coupled to the first input of the first inverter, the second inverter operable to generate a second output signal;
a first switch coupled to the voltage supply and the second supply terminal, the first switch operable to couple the voltage supply to the second supply terminal responsive to an active first read signal;
a second switch coupled to ground and the second ground terminal, the second switch operable to couple ground to the second ground terminal responsive to an active second read signal; and
an access switch coupled to the second output of the second inverter and coupled to the digit line.
9. The memory of claim 8 wherein the first switch comprises a p-channel metal-oxide-semiconductor (PMOS) transistor and the second switch comprises an n-channel metal-oxide-semiconductor (NMOS) transistor.
10. The memory of claim 9 wherein the PMOS transistor comprises a gate to which the first read signal is applied and the NMOS transistor comprises a gate to which the second read signal is applied.
11. The memory of claim 8 wherein the access switch comprises a gate that provides access to the SRAM cell.
12. The memory of claim 8 the access switch comprises a n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the switch signal is applied.
13. The memory of claim 8 wherein the second inverter comprises a complementary metal-oxide-semiconductor (CMOS) inverter coupled to a voltage supply and ground.
14. A method of reading data from a static random access memory cell formed by a pair of cross-coupled inverters, the method comprising:
coupling an output node of one of the cross-coupled inverters to a digit line in response to a signal;
selectively enabling one of the cross-coupled inverters by selectively applying power to the inverter;
enabling a first tri-state inverter to couple the digit line to an intermediate node; and
enabling a second tri-state inverter to couple the intermediate node to an output bus.
15. The method of claim 14 wherein selectively enabling one of the cross-coupled inverters comprises applying an active high logic level to a first switch and an active low logic level to a second switch.
16. The method of claim 14 wherein coupling the output node to the digit line couples a data state latched at the output node to the digit line.
17. A memory comprising:
an array of static random access memory (SRAM) cells, comprising:
a plurality of digit lines;
a plurality of memory cells, each memory cell comprising:
a first inverter having a supply terminal coupled to a voltage supply and a first ground terminal coupled to ground, the first inverter having a first input and a first output, the first inverter operable to generate a first output signal;
a second inverter having a second supply terminal and a second ground terminal, the second inverter having a second input coupled to the first output of the first inverter and a second output coupled to the first input of the first inverter, the second inverter operable to generate a second output signal;
a first switch coupled to the voltage supply and the second supply terminal, the first switch operable to couple the voltage supply to the second supply terminal responsive to an active first read signal;
a second switch coupled to ground and the second ground terminal, the second switch operable to couple ground to the second ground terminal responsive to an active second read signal; and
an access switch coupled to the second output of the second inverter and coupled to the digit line; and
a plurality of sense amplifiers, each sense amplifier comprising a first plurality of tri-state inverters configured to couple a respective one of the plurality of digit lines digit line to an input bus and a second plurality of tri-state inverters configured to couple the respective digit line to an output bus.
18. The memory of claim 17 further comprising a plurality of word lines coupled to the plurality of digit lines.
19. The memory of claim 17 wherein the active first read signal comprises an active high read enable signal and the active second read signal comprises an active low read enable signal.
20. The memory of claim 17 wherein the first inverter comprises a complementary metal-oxide-semiconductor (CMOS) inverter.
21. The memory of claim 17 wherein the first switch comprises a p-channel metal-oxide-semiconductor (PMOS) transistor having a gate to which the first read signal is applied and the second switch comprises an n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the second read signal is applied.
22. The memory of claim 19 wherein the second switch comprises a n-channel metal-oxide-semiconductor (NMOS) transistor having a gate to which the access signal is applied.
23. A memory comprising:
at least one sense amplifier comprising a first plurality of tri-state inverters configured to couple a digit line to an input bus and a second plurality of tri-state inverters configured to couple the digit line to an output bus; and
a static random access memory cell coupled to at least one of the sense amplifiers, comprising:
an inverter;
a tri-state inverter cross coupled to the inverter;
an access transistor coupled to the tri-state inverter and the digit line; and
a control circuit selectively placing the tri-state inverter in tri-state condition responsive to a control signal.
24. The memory of claim 23 wherein the control circuit uses a read signal as the control signal.
25. The memory of claim 23 wherein the tri-state inverter generates an output signal in response to the control signal.