Dielectric extension to mitigate short channel effects
View Patent ↗In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.
1. A method comprising:
patterning a layer of gate electrode material such that apertures are created in the layer of gate electrode material and passivants accumulate on sidewalls of the apertures, wherein the patterning uses a first etching composition;
patterning a layer of gate dielectric material to form openings in the layer of gate dielectric material, wherein the patterning the layer of gate dielectric material leaves behind a portion of the passivants accumulated on the sidewalls of the apertures;
removing at least some of the portion of the passivants accumulated on the sidewalls to create dielectric extensions that extend out into the apertures, wherein the removing the at least some of the portion of the passivants creates dielectric extensions that are configured to retard implantation of dopants into a substrate; and
implanting dopants into a substrate that underlies the layer of gate dielectric material to establish source/drain regions in the substrate, wherein the source/drain regions each have a length that is approximately equal to a distance between adjacent openings in the layer of gate dielectric material so as to have an effect of lengthening a channel of a semiconductor device and mitigating a short channel effect experienced by the semiconductor device.
2. The method of claim 1 , wherein the at least some of the portion of the passivants accumulated on the sidewalls are removed with a wet clean.
3. The method of claim 2 , further comprising:
implanting dopants into the substrate to establish pocket regions under the source/drain regions.
4. The method of claim 2 , further comprising:
forming a layer of hardmask material over the layer of gate electrode material;
patterning the layer of hardmask material; and
patterning the layer of gate electrode material with the patterned layer of hardmask material serving as a mask.
5. The method of claim 2 , further comprising:
performing an anneal to activate the dopants.
6. The method of claim 1 , wherein the at least some of the portion of the passivants accumulated on the sidewalls are removed with a mixture of ammonium hydroxide and hydrogen peroxide.
7. The method of claim 1 , further comprising:
implanting dopants into the substrate to establish pocket regions under the source/drain regions.
8. The method of claim 7 , further comprising:
forming a layer of hard mask material over the layer of gate electrode material;
patterning the layer of hardmask material; and
patterning the layer of gate electrode material with the patterned layer of hardmask material serving as a mask.
9. The method of claim 8 , further comprising:
performing an anneal to activate the dopants.
10. The method of claim 1 , further comprising:
forming a layer of hard mask material over the layer of gate electrode material;
patterning the layer of hard mask material; and
patterning the layer of gate electrode material with the patterned layer of hardmask material serving as a mask.
11. The method of claim 1 , further comprising:
performing an anneal to activate the dopants.
12. The method of claim 1 , further comprising:
switching the first etching composition in situ to a second etching composition, wherein patterning comprises:
patterning the layer of gate dielectric material using the second etching composition.