Generic methodology to support chip level integration of IP core instance constraints in integrated circuits
A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.
1. A method comprising:
selecting an instance of an IP core instantiated in an integrated circuit design, the instance of the IP core representing a block of logic instantiated as a single unit within the integrated circuit represented by the integrated circuit design;
inputting a timing constraints template for the IP core which comprises a plurality of timing constraint statements for inputs and outputs of the IP core, wherein at least one of the statements comprises a configurable variable;
substituting a value for the configurable variable to produce a configured timing constraints template for the instance of the IP core;
generating a set of timing constraints for the instance of the IP core using the configured timing constraints template;
repeating the steps of selecting, inputting, and substituting for each IP core instance in the integrated circuit design that has a timing constraint template having one or more constraint statements with one or more configurable variables;
generating a set of chip-level timing constraints for the integrated circuit, which includes, for each IP core instance, the step of generating the set of timing constraints for the instance using the respective configured timing constraints template for each instance, the set of chip-level timing constraints representing at least one timing requirement of at least one input of the IP core instance;
receiving the set of chip level timing constraints and the configured timing constraints template for each of the IP core instances;
generating a set of golden timing constraints for each of the IP core instances using the respective configured timing constraints template for each instance;
identifying timing constraints in the set of chip level timing constraints that are associated with at least one of the IP core instances; and,
replacing the identified timing constraints with corresponding timing constraints from the sets of golden timing constraints by a computer processor.
2. The method of claim 1 wherein the configurable variable is selected from the group consisting of
a usage mode variable indicating a functional usage of the IP core instance in the integrated circuit design;
a reference frequency variable;
an instantiation mode variable indicating a mode in which the IP core instance is instantiated in the integrated circuit design;
a bit mode variable indicating a number of bits in a set of the inputs or outputs for the IP core instance;
a hierarchy variable indicating a hierarchy at which the IP core instance is instantiated within the integrated circuit design;
a clock prefix variable indicating a unique clock prefix to be associated with one or more of the inputs or outputs for the IP core instance; and
a port name variable indicating a unique name to be associated with one or more of the inputs or outputs for the IP core instance.
3. The method of claim 1 and further comprising:
inputting metadata, which defines one or more attributes of the configurable variable;
producing a graphical user interface based on the metadata, which enables a user to associate the value with the configurable variable; and
receiving the value from the graphical user interface and performing the step of substituting using the received value.
4. A method of generating a set of chip-level timing constraints, comprising:
selecting an instance of an IP core instantiated in an integrated circuit design, the instance of the IP core representing a block of logic instantiated as a single unit within the integrated circuit represented by the integrated circuit design;
receiving a timing constraints template for the IP core that comprises a plurality of timing constraint statements for inputs and outputs of the IP core, wherein at least one of the statements comprises a configurable variable;
setting a value for the configurable variable to produce a configured timing constraints template for the instance of the IP core;
generating a set of timing constraints for the instance of the IP core using the configured timing constraints template;
generating a set of chip-level timing constraints for the integrated circuit, which includes, for the IP core instance, the step of generating the set of timing constraints for the instance using the respective configured timing constraints template for the instance, the set of chip-level timing constraints representing at least one timing requirement of at least one input of the IP core instance;
receiving the set of chip level timing constraints and the configured timing constraints template for the IP core instance;
generating a set of golden timing constraints for the IP core instance using the respective configured timing constraints template for the instance;
identifying timing constraints in the set of chip level timing constraints that are associated with the IP core instance; and,
replacing the identified timing constraints with corresponding timing constraints from the set of golden timing constraints by a computer processor.
5. The method of claim 4 wherein the configurable variable is selected from the group consisting of
a usage mode variable indicating a functional usage of the IP core instance in the integrated circuit design;
a reference frequency variable;
an instantiation mode variable indicating a mode in which the IP core instance is instantiated in the integrated circuit design;
a bit mode variable indicating a number of bits in a set of the inputs or outputs for the IP core instance;
a hierarchy variable indicating a hierarchy at which the IP core instance is instantiated within the integrated circuit design;
a clock prefix variable indicating a unique clock prefix to be associated with one or more of the inputs or outputs for the IP core instance; and
a port name variable indicating a unique name to be associated with one or more of the inputs or outputs for the IP core instance.
6. The method of claim 4 further comprising:
inputting metadata, which defines one or more attributes of the configurable variable;
producing a graphical user interface based on the metadata, which enables a user to associate the value with the configurable variable; and
receiving the value from the graphical user interface and performing the step of substituting using the received value.