Low operating voltage electro-static discharge device and method

1. An apparatus that discharges an electrostatic charge, the apparatus comprising:

a semiconductor integrated circuit, the semiconductor integrated circuit including:

an input;

a ground connection that provides a discharge path for the electrostatic charge; and

an electrostatic discharge device connected between the input and the ground connection that has low leakage at an operating voltage, a positive trigger voltage, a positive clamping voltage, and wherein the positive clamping voltage is substantially independent of the positive trigger voltage, such that the device turns on in order to dissipate the electrostatic charge, the device including:

an N+ substrate region that is connected to the ground connection,

a P epitaxial region that is formed over the N+ anode region that has a thickness and a doping concentration that together substantially determine the positive clamping voltage, and

an N+ electrode region that is formed within the P epitaxial region, such that a side wall surface of the N+ electrode region around a side wall surface of the P epitaxial region, the N+ electrode region connected to the input; and

a P+ sidewall region formed over the P epitaxial region in a continuous region adjacent the sidewall surface of the N+ electrode region, wherein the P+ sidewall region and the N+ electrode form a zener diode that injects current into the P epitaxial region and thereby causes turn-on of a transistor formed by the N+ electrode region, the P region and the N+ substrate region, wherein a concentration of the P+ sidewall region assists in determining the positive trigger voltage without substantially having an effect on the positive clamping voltage.

2. The apparatus according to claim 1 wherein the P− region is linearly graded.

3. The apparatus according to claim 2 wherein a doping of the linearly graded P-region ranges from 1E16/cm3 to 1E18/cm3.

4. The apparatus according to claim 3 wherein a width of the linearly graded P-region ranges from 1 to 4 um.

5. The apparatus according to claim 1 further including a thermal oxide disposed over the P+ sidewall region.

6. The apparatus according to claim 1 wherein the positive trigger voltage is less than about 5 volts.

7. The apparatus according to claim 6 wherein the positive trigger voltage lasts for less than about 10 nanoseconds.

8. The apparatus according to claim 1 wherein the low leakage is less than about 100 NanoAmps.

9. The apparatus according to claim 8 wherein the operative voltage is less than about 5 volts.

10. An apparatus that discharges an electrostatic charge, the apparatus comprising:

a semiconductor integrated circuit, the semiconductor integrated circuit including:

an input;

a ground connection that provides a discharge path for the electrostatic charge;

an electrostatic discharge device connected between the input and the ground connection that has low leakage at an operating voltage, a positive trigger voltage, a negative trigger voltage, a positive clamping voltage, and a negative clamping voltage, and wherein the positive and the negative clamping voltages are substantially independent of the positive and the negative trigger voltages, such that the device turns on in order to dissipate the electrostatic charge, the device including:

an N+ substrate region that is connected to the ground connection,

a P epitaxial region that is formed over the N+ anode region that has a thickness and a doping concentration that together substantially determine the positive and negative clamping voltages, and

an N+ electrode region that is formed within the P epitaxial region, such that a side wall surface of the N+ cathode region around a side wall surface of the P epitaxial region, the N+ electrode region connected to the input;

a P+ sidewall region formed over the P epitaxial region in a continuous region between a portion of the sidewall surface of the N+ substrate region and a portion of the sidewall surface of the N+ electrode region; and

an N+ region that extends between the P+ sidewall region and the N+ substrate region;

wherein the P+ sidewall region and the N+ cathode form a positive zener diode that injects positive current into the P epitaxial region and thereby causes turn-on of a transistor formed by the N+ electrode region, the P epitaxial region and the N+ substrate region,

wherein the P+ sidewall region and the N+ region form a negative zener diode that injects negative current into the P epitaxial region and thereby causes turn-on of a transistor formed by the N+ electrode region, the P epitaxial region and the N+ substrate region, and

wherein a P+ concentration of the P+ sidewall region assists in determining the positive and the negative trigger voltages without substantially having an effect on the positive and the negative clamping voltages.

11. The apparatus according to claim 10 wherein the P− region is linearly graded.

12. The apparatus according to claim 11 wherein a doping of the linearly graded P-region ranges from 1E16/cm3 to 1E18/cm3.

13. The apparatus according to claim 12 wherein a width of the linearly graded P-region ranges from 1 to 4 um.

14. The apparatus according to claim 1 wherein the positive trigger voltage is less than about 5 volts and the negative trigger voltage is greater than about −5 volts.

15. The apparatus according to claim 14 wherein the positive trigger voltage lasts for less than about 10 nanoseconds and the negative trigger voltage lasts for less than about 10 nanoseconds.

16. The apparatus according to claim 10 wherein the low leakage is less than about 100 NanoAmps.

17. The apparatus according to claim 16 wherein the operative voltage is less than about 5 volts.