Multi-phase wordline erasing for flash memory
View Patent ↗Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
1. A system, comprising:
a storage component that includes a plurality of wordlines that store information;
a receiving component that receives a command to erase information stored in the storage component; and
an erasing component that erases information stored on the plurality of wordlines in a sequence of at least two phases, wherein each phase of the sequence includes a subset of the plurality of wordlines, and wherein the sequence is based at least in part on location or spacing of the plurality of wordlines in the storage component, and the sequence is further based at least in part upon: a new sequence responding to the command, a predetermined sequence from a look-up table, or a sequence included as part of the command.
2. The system of claim 1 , further comprising a regulator component that creates the sequence for use by the erasing component.
3. The system of claim 1 , further comprising a logging component that creates a record of erasing component operation.
4. The system of claim 1 , further comprising an analysis component that determines whether the erasing component uses a sequence included with the command.
5. The system of claim 1 , further comprising a gate component that commences starting time of at least one phase.
6. The system of claim 1 , further comprising a notification component that sends a message about the erasing component to an external device or to a diagnostic component within the system.
7. The system of claim 1 , wherein the erasing component comprises a memory component that includes the sequence for erasing information stored on the plurality of wordlines.
8. The system of claim 1 , further comprising a computation component that calculates how many bitlines should be erased from a plurality of bitlines during each phase.
9. The system of claim 8 , wherein the erasing component erases information stored on a number of bitlines during each phase wherein erased bitlines for each phase are calculated by the computation component.
10. The system of claim 1 , wherein the sequence is determined based upon proximity of a wordline to a contact in the storage component.
11. The system of claim 1 , wherein the sequence is determined based upon spatial distance between neighboring wordlines.
12. A method, comprising:
receiving a command to erase information stored in wordlines of a flash memory device;
obtaining a multi-stage sequence for erasing wordlines based on location and spacing of the wordlines within the flash memory device, wherein a stage includes one or more wordlines and the multi-stage sequence includes at least one of: a multi-stage sequence created in response to the command, a pre-set multi-stage sequence from a look-up table, or a multi-stage sequence that is based at least in part on an erase sequence included in the command; and
implementing the multi-stage sequence for erasing wordlines.
13. The method of claim 12 , further comprising calculating bitlines to erase for at least one state of the multi-stage sequence.
14. The method of claim 13 , wherein implementing a multi-stage sequence comprises erasing calculated bitlines.
15. The method of claim 12 , further comprising making a documentation of implementing the multi-stage sequence.
16. The method of claim 12 , further comprising determining whether to implement an obtained multi-stage sequence based at least in part on an erase sequence included in the command.
17. The method of claim 12 , further comprising distributing a correspondence about implementing the multi-stage sequence.
18. The method of claim 12 , wherein implementing the multi-stage sequence includes starting a second stage before completion of a first stage.
19. The method of claim 12 , wherein the multi-stage sequence is obtained from a component that creates a multi-stage sequence.
20. A system, comprising:
means for holding information in a plurality of bitlines and a plurality of wordlines;
means for receiving a command to erase information held on the plurality of bitlines and the plurality of wordlines; and
means for expunging information held on the plurality of wordlines and the plurality of bitlines through a multi-stage progression, the multi-stage progression is based at least in part on the distance between adjacent wordlines from the plurality of wordlines and is at least one of: created for the command, a pre-set sequence, progression information included in the command, or a hybrid comprising a pre-set sequence and progression information included in the command.