Circuit system with circuit element and reference plane
View Patent ↗A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.
1. A method of manufacturing a circuit system comprising:
forming a lower electrode over a substrate;
forming a resistive film directly on the lower electrode;
forming a multi-layered insulating stack over the resistive film with a top surface of the resistive film partially exposed from the multi-layered insulating stack, the multi-layered insulating stack in direct contact with and covering a vertical side of the resistive film; and
depositing an upper electrode over the multi-layered insulating stack.
2. The method as claimed in claim 1 wherein forming the multi-layered insulating stack includes forming dissimilar layers of dielectric films.
3. The method as claimed in claim 1 further comprising:
forming a further multi-layered insulating stack over the resistive film with a gap between the multi-layered insulating stack and the further multi-layered insulating stack; and
forming the upper electrode over a portion of the further multi-layered insulating stack.
4. The method as claimed in claim 1 wherein forming the upper electrode includes forming a reference plane.
5. The method as claimed in claim 1 wherein forming the multi-layered insulating stack includes covering sides of the lower electrode.
6. A method of manufacturing a circuit system comprising:
forming a lower electrode over a substrate;
forming a resistive film directly on the lower electrode;
forming multi-layered insulating stacks over the resistive film with a gap between each of the multi-layered insulating stacks with a top surface of the resistive film partially exposed from the multi-layered insulating stacks, portions of the multi-layered insulating stacks in direct contact with and covering a vertical side of the resistive film; and
depositing an upper electrode over each of the multi-layered insulating stacks.
7. The method as claimed in claim 6 wherein forming the multi-layered insulating stacks includes:
forming a bottom dielectric film comprised of oxide over the resistive film in each of the multi-layered insulating stacks; and
forming a top dielectric film comprised of nitride over the bottom dielectric film in each of the multi-layered insulating stacks.
8. The method as claimed in claim 6 wherein forming the multi-layered insulating stacks separated by the gap includes forming a growth region for the lower electrode under the gap.
9. The method as claimed in claim 6 wherein forming the multi-layered insulating stacks separated by the gap includes not connecting the lower electrode and the upper electrode under the multi-layered insulating stacks.
10. The method as claimed in claim 6 wherein forming the lower electrode over the substrate includes forming the lower electrode over an integrated circuit substrate, an integrated circuit package substrate, or a printed circuit board.
11. A circuit system comprising:
a substrate;
a lower electrode over the substrate;
a resistive film directly on the lower electrode;
a multi-layered insulating stack over the resistive film with a top surface of the resistive film partially exposed from the multi-layered insulating stack, the multi-layered insulating stack in direct contact with and covering a vertical side of the resistive film; and
an upper electrode over the multi-layer insulating stack.
12. The system as claimed in claim 11 wherein the multi-layered insulating stack includes dissimilar layers of dielectric films.
13. The system as claimed in claim 11 further comprising:
a further multi-layered insulating stack over the resistive film with a gap between the multi-layered insulating stack and the further multi-layered insulating stack; and
the upper electrode over a portion of the further multi-layered insulating stack.
14. The system as claimed in claim 11 wherein the upper electrode includes a reference plane.
15. The system as claimed in claim 11 wherein the multi-layered insulating stack is over sides of the lower electrode.
16. The system as claimed in claim 11 wherein:
the upper electrode includes a ground plane; and
further comprising:
a further multi-layered insulating stack over the resistive film with a gap between the multi-layered insulating stack and the further multi-layered insulating stack; and
the upper electrode over a portion of the further multi-layered insulating stack.
17. The system as claimed in claim 16 wherein forming the multi-layered insulating stack includes:
a first bottom dielectric film comprised of oxide over the resistive film; and
a first top dielectric film comprised of nitride over the first bottom dielectric film.
18. The system as claimed in claim 16 wherein the gap between the multi-layered insulating stack and the further multi-layered insulating stack includes a growth region for the lower electrode under the gap.
19. The system as claimed in claim 16 wherein the gap between the multi-layered insulating stack and the further multi-layered insulating stack includes the lower electrode and the upper electrode not connected under the multi-layered insulating stack and the further multi-layered insulating stack.
20. The system as claimed in claim 16 wherein the substrate includes an integrated circuit substrate, an integrated circuit package substrate, or a printed circuit board.