IP Library › Granted Patent US 7,646,062
Granted Patent B2
US 7,646,062 · App. 11/770,337 · Granted Jan 12, 2010

Semiconductor device comprising buried wiring layer

Assignee: Sanyo Electric Co., Ltd.
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Quick Facts
Patent No.
US 7,646,062
App. No.
11/770,337
Granted
Jan 12, 2010
Kind
B2
Abstract

A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.

Claims (38)

1. A semiconductor device comprising:

a semiconductor substrate having a surface;

a wiring layer buried in the semiconductor substrate;

a conductor buried in the semiconductor substrate and made of a metallic material or polysilicon, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate; and

an insulation film arranged between the semiconductor substrate and the conductor, wherein the first end of the conductor extends into the wiring layer from an end of the insulation film and the second end of the conductor extends outward from the surface of the semiconductor substrate,

wherein the wiring layer includes a groove that comes in contact with the first end of the conductor.

2. The semiconductor device according to claim 1 , wherein the insulation film is in contact with the semiconductor substrate.

3. The semiconductor device according to claim 1 , further comprising:

a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.

4. The semiconductor device according to claim 1 , wherein:

the insulation film, which has a surface, further covers the surface of the semiconductor substrate; and

said part of the conductor is higher than the surface of the insulation film.

5. The semiconductor device according to claim 1 , wherein the conductor has at least one first plane and at least one second plane that are alternately arranged adjacent to each other, with the adjacent first and second planes being angled from each other at an obtuse angle.

6. The semiconductor device according to claim 1 , wherein the part of the conductor includes a curved surface.

7. A semiconductor device comprising:

a semiconductor substrate;

a wiring layer buried in the semiconductor substrate;

a conductor buried in the semiconductor substrate, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate; and

an insulation film arranged between the semiconductor substrate and the conductor, wherein the conductor has at least one first plane and at least one second plane that are arranged adjacent to each other, with the second plane having a part that is not in contact with the insulation film, wherein the adjacent first and second planes of the conductor form therebetween an inflection point at which the adjacent first and second planes are angled from each other at an obtuse angle.

8. The semiconductor device according to claim 7 , wherein the insulation film is in contact with the semiconductor substrate.

9. The semiconductor device according to claim 7 , further comprising:

a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.

10. The semiconductor device according to claim 7 , wherein the conductor includes a curved upper surface.

11. The semiconductor device according to claim 7 , wherein the wiring layer includes a groove that comes in contact with part of the conductor.

12. A semiconductor device comprising:

a semiconductor substrate having a surface;

a wiring layer buried in the semiconductor substrate;

a conductor buried in the semiconductor substrate, with the conductor having a first end connected to the wiring layer and a second end exposed from the semiconductor substrate;

a gate electrode buried in the semiconductor substrate, wherein a part of the semiconductor substrate is arranged between the conductor and the gate electrode; and

an insulation film arranged between the semiconductor substrate and the conductor, wherein the second end of the conductor extends outward from the surface of the semiconductor substrate,

wherein the wiring layer includes a groove that comes in contact with the first end of the conductor.

13. The semiconductor device according to claim 12 , further comprising:

a conductive layer formed on the semiconductor substrate, wherein current flows between the conductor, the wiring layer, the semiconductor substrate, and the conductive layer.

14. The semiconductor device according to claim 12 , wherein:

the insulation film, which has a surface, further covers the surface of the semiconductor substrate; and

said part of the conductor is higher than the surface of the insulation film.

15. The semiconductor device according to claim 12 , wherein the conductor has at least one first plane and at least one second plane that are alternately arranged adjacent to each other, with the adjacent first and second planes being angled from each other at an obtuse angle.

16. The semiconductor device according to claim 12 , wherein the part of the conductor includes a curved surface.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 19, 2007
From: YAMAOKA, YOSHIKAZU; SHIMADA, SATORU
To: SANYO ELECTRIC CO., LTD.
Reel/Frame 019846/0409 →
Priority Claims (2)
JP 2006-179119 · Jun 29, 2006 · national
JP 2007-141961 · May 29, 2007 · national
Continuity (1)
Related Publication 20080001214A1 · Jan 3, 2008