Semiconductor test structures
View Patent ↗Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
1. A semiconductor structure, comprising:
a first test structure comprising:
a first instance of a first feature, and
a first instance of a second feature above and aligned with the first instance of the first feature;
a second test structure comprising:
at least one of:
a second instance of the first feature not aligned with an instance of the second feature, and
a second instance of the second feature not aligned with an instance of the first feature,
the first and second instances of the first feature in a first layer and the first and second instances of the second feature in a second layer over the first layer;
a first reference mark in the first layer coincident with a reference mark in a first underlaying layer; and
a second reference mark in the second layer coincident with a reference mark in a second underlaying layer and not aligned with the first reference mark.
2. The structure of claim 1 , the second underlaying layer corresponding to the first layer.
3. The structure of claim 2 , comprising:
a first pattern in the first layer comprising at least one feature corresponding to the first feature of the first test structure; and
a second pattern in the second layer comprising at least one feature corresponding to the second feature of the first test structure and aligned with the at least one feature corresponding to the first feature of the first test structure.
4. The structure of claim 3 , the first layer comprising polysilicon formed to a thickness of between about 100 nanometers and about 400 nanometers and the second layer comprising metal oxide formed to a thickness of between about 1 nanometer and about 10 nanometers.
5. The structure of claim 1 , comprising:
a first pattern in the first layer comprising at least one feature corresponding to the first feature of the first test structure; and
a second pattern in the second layer comprising at least one feature corresponding to the second feature of the first test structure and aligned with the at least one feature corresponding to the first feature of the first test structure.
6. The structure of claim 1 , the first layer comprising polysilicon.
7. The structure of claim 6 , the first layer formed to a thickness of between about 100 nanometers and about 400 nanometers.
8. The structure of claim 1 , the first layer formed to a thickness of between about 100 nanometers and about 400 nanometers.
9. The structure of claim 1 , the second layer comprising metal oxide.
10. The structure of claim 9 , the second layer formed to a thickness of between about 1 nanometer and about 10 nanometers.
11. The structure of claim 1 , the second layer formed to a thickness of between about 1 nanometer and about 10 nanometers.
12. The structure of claim 1 , comprising:
a first target overlay mark and a first measured overlay mark in the first layer, the first measured overlay mark coincident with a corresponding target overlay mark in an underlaying layer; and
a second measured overlay mark in the second layer coincident with the first target overlay mark.
13. The structure of claim 12 , comprising:
a first pattern in the first layer comprising at least one feature corresponding to the first feature of the first test structure; and
a second pattern in the second layer comprising at least one feature corresponding to the second feature of the first test structure and aligned with the at least one feature corresponding to the first feature of the first test structure.
14. The structure of claim 13 , comprising:
a second target overlay mark in the second layer coincident with a subsequently formed measured overlay mark formed in a subsequent layer.
15. The structure of claim 14 , the first layer comprising polysilicon formed to a thickness of between about 100 nanometers and about 400 nanometers and the second layer comprising metal oxide formed to a thickness of between about 1 nanometer and about 10 nanometers.
16. A semiconductor structure, comprising:
first and second test structures in a first layer;
third and fourth test structure in a second layer over the first layer, the third test structure aligned with the first test structure and the fourth test structure not aligned with the second test structure;
a first reference mark in the first layer coincident with a reference mark in a first underlaying layer; and
a second reference mark in the second layer coincident with a reference mark in a second underlaying layer and not aligned with the first reference mark.
17. The structure of claim 16 , comprising:
a first pattern in the first layer comprising at least one feature corresponding to the first test structure; and
a second pattern in the second layer comprising at least one feature corresponding to the third test structure and aligned with the at least one feature corresponding to the first test structure.