IP Library Granted Patent US 7,479,703
Granted Patent B1
US 7,479,703 · App. 11/772,267 · Granted Jan 20, 2009

Integrated circuit package with sputtered heat sink for improved thermal performance

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Quick Facts
Patent No.
US 7,479,703
App. No.
11/772,267
Granted
Jan 20, 2009
Kind
B1
Abstract

An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.

Claims (32)

1. An integrated circuit package comprising:

an integrated circuit die having a circuit surface and a back surface opposite the circuit surface; and

a layer of ductile material deposited on the back surface of the integrated circuit die, the layer of ductile material having a thickness of from one to five microns; and

solder bumps formed on the circuit surface of the integrated circuit die to electrically connect the integrated circuit die to a package substrate.

2. An integrated circuit package comprising:

an integrated circuit die having a circuit surface and a back surface opposite the circuit surface;

a layer of ductile material deposited on the back surface of the integrated circuit die, the layer of ductile material having a thickness of from one to five microns; and

an identification mark on the layer of ductile material.

3. An integrated circuit package comprising:

an integrated circuit die having a circuit surface and a back surface opposite the circuit surface; and

a layer of ductile material deposited on the back surface of the integrated circuit die, the layer of ductile material having a thickness of from one to five microns and comprising one of titanium, aluminum, copper, and gold.

4. An integrated circuit package comprising:

an integrated circuit die having a circuit surface and a back surface opposite the circuit surface; and

a layer of ductile material deposited on the back surface of the integrated circuit die, the layer of ductile material having a thickness of from one to five microns and formed to conduct heat from the integrated circuit die.

5. An integrated circuit package comprising:

an integrated circuit die having a circuit surface and a back surface opposite the circuit surface; and

a layer of ductile material deposited on the back surface of the integrated circuit die, the layer of ductile material having a thickness of from one to five microns and formed to relieve tensile stress from the integrated circuit die.

6. A method of making an integrated circuit package comprising steps of:

providing an integrated circuit die having a circuit surface and a back surface opposite the circuit surface;

depositing a layer of ductile material on the back surface of the integrated circuit die, the layer of ductile material deposited to a thickness of from one to five microns; and

forming solder bumps on the circuit surface of the integrated circuit die to electrically connect the integrated circuit die to a package substrate.

7. A method of making an integrated circuit package comprising steps of:

providing an integrated circuit die having a circuit surface and a back surface opposite the circuit surface;

depositing a layer of ductile material on the back surface of the integrated circuit die, the layer of ductile material deposited to a thickness of from one to five microns; and

making an identification mark on the layer of ductile material.

8. The method of claim 6 further comprising a step of depositing the layer of ductile material comprising one of titanium, aluminum, copper, and gold.

9. The method of claim 6 further comprising a step of forming the layer of ductile material to conduct heat from the integrated circuit die.

10. The method of claim 6 further comprising a step of forming the layer of ductile material to relieve tensile stress from the integrated circuit die.

11. An integrated circuit die comprising:

a circuit surface and a back surface opposite the circuit surface;

a layer of ductile material deposited on the back surface; and

an identification mark on the layer of ductile material.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2007
From: KUTLU, ZAFER
To: LSI LOGIC CORPORATION
Reel/Frame 019503/0549 →