Semiconductor device having improved wiring
View Patent ↗An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball ( 5 ), no ordinary wiring line is formed in a region ( 7 (A)) in the vicinity of the support ball ( 5 ) and a region ( 7 (B)) at the end of the semiconductor chip facing the support ball ( 5 ), which are the stress concentration regions of the package substrate ( 2 ). Instead, a wiring line ( 6 (C)) is formed away from these regions or a wide wiring line is formed in these regions.
1. An electronic component having an electronic element chip mounted on a package substrate, comprising:
a first ball for supporting the package substrate, the first ball being disposed on a surface of the package substrate inside a first region wherein the package substrate and the electronic element chip are coextensive; and
a second ball for supporting the package substrate, the second ball disposed on the package substrate outside the first region;
a plurality of wiring lines with an ordinary width formed on the package substrate inside the first region extending from said first region to a second region outside of the first region,
wherein none of the wiring lines are formed in a third region substantially above the second ball.
2. The electronic component according to claim 1 , comprising a module substrate fixing the package substrate by means of the first ball and the second ball.
3. The electronic component according to claim 1 , wherein none of the wiring lines are formed in a fourth region substantially below a border of the first region at a position adjacent the second ball.
4. The electronic component according to claim 3 , wherein the first ball is a signal ball for conducting electricity, and the second ball is a support ball.
5. The electronic component according to claim 4 , wherein the support ball is arranged outwardly away from the border of the first region by a distance corresponding to a diameter of a ball land provided for the support ball on the package substrate.
6. The electronic component according to claim 5 , wherein the third region has dimensions corresponding to two ball lands on the surface of the package substrate extending from the center of the support ball in a first direction away from the border of the first region and corresponding to three ball lands on the surface of the package substrate including one ball land each extending vertically up and down from the support ball in a second direction orthogonal to the first direction.
7. The electronic component according to claim 6 , wherein the second region has dimensions corresponding to one ball land on the surface of the package substrate in the first direction and corresponding to three ball lands on surface of the package substrate in the second direction, with the center of the fourth region being positioned on the border of the first region.
8. The electronic component according to any of claims 4 to 7 , wherein a wide wiring line with a width greater than an ordinary width is disposed adjacent to the first and second regions.
9. The electronic component according to any of claims 4 to 7 , wherein a wide wiring line with a width greater than an ordinary width is disposed in the second region.
10. The electronic component according to any of claims 4 to 7 , wherein a wide wiring line with a width greater than an ordinary width is disposed in the first and second regions.
11. The electronic component according to claim 8 , wherein the wide wiring line is a power supply wiring line, a ground wiring line, or a reference voltage wiring line.
12. The electronic component according to claim 10 , wherein the wide wiring line has a width of 200 μm or greater.
13. The electronic component according to claim 1 , comprising an upper package stacked above the package, wherein the upper package comprises:
an upper package substrate having an electronic element chip mounted thereon;
upper package substrate supporting means disposed on the rear surface of the upper package corresponding to the inside of the contour defined by the outline of the electronic element chip; and
a signal ball located outside the contour defined by the outline of the electronic element chip to support the upper package substrate, and
wherein no wiring line with an ordinary width is formed in a first region on the surface of the upper package substrate corresponding to the vicinity of the position of the signal ball or a second region located on the surface of the upper package substrate in the vicinity of the contour defined by the outline of the electronic element chip.
14. The electronic component according to claim 13 , wherein the upper package supporting means is an adhesive applied to fill the space between the package and the upper package.
15. The electronic component according to claim 13 , wherein the upper package supporting means is a signal ball disposed between the package and the upper package.
16. The electronic component according to claim 14 or 15 , wherein a wide wiring line with a width greater than an ordinary width is disposed close to the first and second regions of the upper package.
17. The electronic component according to claim 14 or 15 , wherein a wide wiring line with a width greater than an ordinary width is disposed in the second region of the upper package.
18. The electronic component according to claim 14 or 15 , wherein a wide wiring line with a width greater than an ordinary width is disposed in the first and second regions of the upper package.
19. An electronic component comprising:
a substrate;
an electronic chip mounted on the substrate;
a first ball disposed on the substrate within a first region of the substrate that is coextensive with the electronic chip;
a second ball disposed on the substrate outside of the first region; and
a plurality of wiring lines having a width of 100 μm or less formed on the substrate, extending from a position inside the first region to a position inside a second region outside the first region,
wherein none of the wiring lines extend substantially in the vicinity of the second ball.
20. The electronic component according to claim 1 , wherein the first ball and the second ball are disposed on a rear surface of the package substrate.
21. The electronic component according to claim 1 , wherein the wiring lines comprise surface layer wiring lines formed on the package substrate.