IP Library Granted Patent US 7,861,235
Granted Patent B2
US 7,861,235 · App. 11/822,730 · Granted Dec 28, 2010

Program control device and program control method

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Quick Facts
Patent No.
US 7,861,235
App. No.
11/822,730
Granted
Dec 28, 2010
Kind
B2
Abstract

Disclosed is a program control device for managing cache information and generating an optimum linker option to thereby improve use efficiency of a cache memory. A cache line information generating section is formed which, when a target program is loaded into a main memory, generates cache line information. Therefore, the cache line information having memory address information and symbolic information in a function of the target program in a cache line can be displayed with cache performance information. Accordingly, functions causing a cache conflict can be easily specified and rearranged by a linker option so as not to share the same cache line. As a result, the cache misses can be reduced.

Claims (32)

1. A program control device for managing cache information and performing program control, comprising:

a building section for converting a received source program into a target program by a build process;

a memory loading section for loading the target program into a main memory;

a cache line information generating section for generating cache line information having symbolic information and memory address information of the target program;

a cache performance information generating section for generating cache performance information having a cache hit rate and cache miss rate of the target program;

a cache information merging section for merging the cache line information and the cache performance information to generate cache information; and

a cache information displaying section for displaying the cache information.

2. The program control device according to claim 1 , wherein:

in the cache line information generating section, functions in the target program are discriminated with the cache line information, the program sharing the same cache line; and

in the cache information displaying section, the discriminated functions are displayed with the cache information.

3. The program control device according to claim 2 , further comprising:

an arrangement control section for rearranging the functions using the discriminated functions and the cache information;

an address calculating section for calculating an address after the rearrangement; and

a linker option generating section for generating a linker option for the rearrangement.

4. The program control device according to claim 3 , wherein one of a drug and drop operation and a specific algorithm is used for the rearrangement.

5. The program control device according to claim 2 , wherein the functions are highlighted.

6. A program control method for managing cache information and performing program control, comprising:

a building step of converting a received source program into a target program by a build process;

a memory loading step of loading the target program into a main memory;

a cache line information generating step of generating cache line information having symbolic information and memory address information of the target program;

a cache performance information generating step of generating cache performance information having a cache hit rate and cache miss rate of the target program;

a cache information merging step of merging the cache line information and the cache performance information to generate cache information; and

a cache information displaying step of displaying the cache information.

7. The method according to claim 6 , wherein:

in the cache line information generating step, functions in the target program, which share the same cache line, are discriminated with the cache line information; and

in the cache information displaying step, the discriminated functions are displayed with the cache information.

8. The method according to claim 7 , further comprising:

an arrangement control step of rearranging the functions using the discriminated functions and the cache information;

an address calculating step of calculating an address after the rearrangement; and

a linker option generating step of generating a linker option for the rearrangement.

9. The method according to claim 8 , wherein one of a drug and drop operation and a specific algorithm is used for the rearrangement.

10. The method according to claim 7 , wherein the functions are highlighted.

Assignments (10)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 27, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024794/0500 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021985/0715 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2007
From: WATANABE, MANABU
To: FUJITSU LIMITED
Reel/Frame 019592/0076 →