Method of manufacturing integrated circuit package system with warp-free chip

1. A method of manufacturing an integrated circuit package system comprising:

providing an integrated circuit wafer having a backside;

forming a stress-relieving layer on the backside of the integrated circuit wafer;

forming an adhesion layer on the stress-relieving layer;

dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer over the backside of the semiconductor chip; and

mounting the semiconductor chip including the stress-relieving layer on the backside and the adhesion layer on electrical interconnects.

2. The method as claimed in claim 1 wherein:

forming the adhesion layer forms the adhesion layer on selected regions of the stress-relieving layer;

dicing the integrated circuit wafer leaves portions of the adhesion layer only adjacent the diced sides of the semiconductor chip; and

mounting the semiconductor chip mounts the portions of the adhesion layer on the electrical interconnects.

3. The method as claimed in claim 1 wherein:

forming the adhesion layer forms the adhesion layer thicker than the stress-relieving layer; and

mounting the semiconductor chip mounts the adhesion layer on the electrical interconnects and over the sides thereof.

4. The method as claimed in claim 1 further comprising:

forming an additional stress-relieving layer on the adhesion layer; and

mounting the semiconductor chip mounts the additional stress-relieving layer on the electrical interconnects.

5. The method as claimed in claim 1 further comprising:

electrically connecting the semiconductor chip to the electrical interconnects with bond wires; and

encapsulating the semiconductor chip, the bond wires, and the electrical interconnects with portions of the electrical interconnects exposed.

6. A method of manufacturing an integrated circuit package system comprising:

providing an integrated circuit wafer having an active side and a backside;

forming a low modulus stress-relieving layer on the backside of the integrated circuit wafer;

forming a high modulus adhesion layer on the low modulus stress-relieving layer;

fully or partially curing the low modulus stress-relieving layer or the high modulus adhesion layer;

dicing the integrated circuit wafer into a semiconductor chip with the low modulus stress-relieving layer and the high modulus adhesion layer over the backside of the semiconductor chip; and

mounting the semiconductor chip including the low modulus stress-relieving layer on the backside and the high modulus adhesion layer on leadfingers.

7. The method as claimed in claim 6 wherein:

forming the high modulus adhesion layer forms the high modulus adhesion layer on selected regions of the low modulus stress-relieving layer;

dicing the integrated circuit wafer leaves portions of the high modulus adhesion layer only adjacent the diced sides of the semiconductor chip; and

mounting the semiconductor chip mounts the portions of the high modulus adhesion layer on the leadfingers.

8. The method as claimed in claim 6 wherein:

forming the high modulus adhesion layer forms the high modulus adhesion layer thicker than the low modulus stress-relieving layer; and

mounting the semiconductor chip mounts the high modulus adhesion layer on the leadfingers and bonded to the sides thereof.

9. The method as claimed in claim 6 further comprising:

forming an additional low modulus stress-relieving layer on the high modulus adhesion layer; and

mounting the semiconductor chip mounts the additional low modulus stress-relieving layer on the leadfingers.

10. The method as claimed in claim 6 further comprising:

electrically connecting the semiconductor chip to the leadfingers with bond wires; and

encapsulating the semiconductor chip, the bond wires, and the leadfingers with portions of the leadfingers exposed.