IP Library Granted Patent US 7,582,949
Granted Patent B2
US 7,582,949 · App. 11/870,567 · Granted Sep 1, 2009

Semiconductor devices

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Quick Facts
Patent No.
US 7,582,949
App. No.
11/870,567
Granted
Sep 1, 2009
Kind
B2
Abstract

A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The design structure additionally includes a reach-through structure connecting the first and second sub-collectors, and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. Also, the design structure includes N+ diffusion regions in contact with the N-well, a P+ diffusion region within the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.

Claims (11)

1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer;

a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer;

a reach-through structure connecting the first and second sub-collectors;

an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure;

N+ diffusion regions in contact with the N-well;

a P+ diffusion region within the N-well; and

shallow trench isolation structures between the N+ and P+ diffusion regions.

2. The design structure of claim 1 , wherein the design structure comprises a netlist, which describes the circuit.

3. The design structure of claim 1 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →