Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design
View Patent ↗An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least one phase-shifted sub-domain clock for each block, assigning primary inputs and primary outputs of the block to the root clock, assigning non-primary inputs and non-primary outputs of the block to the sub-domain clock, splitting root clock inputs into root clock inputs and phase-shifted sub-domain clock inputs, assigning each of the blocks a different phase-shifted sub-domain clock phase offset, creating a clock generation circuitry for the root clocks and the phase-shifted sub-domain clocks.
1. A design structure embodied in a machine readable non-transient medium used in a design process, the design structure comprising a system for noise reduction in an electrical circuit comprising:
a synthesizer to synthesize blocks comprising sequential elements in said electrical circuit;
a generator to operate on said sequential elements to generate a root clock signal and at least one phase-shifted sub-domain clock signal for each of said blocks;
a first assignment unit to act on said blocks adapted to assign primary inputs and primary outputs of said block to said root clock signal;
a second assignment unit to act on said blocks to assign non-primary inputs and non-primary outputs of said block assigned to said phase-shifted sub-domain clock signal; and
an allocator connected to said generator to allocate said blocks comprising different phase-shifted sub-domain clock signals.
2. The design structure according to claim 1 , wherein said sequential elements comprise boundary elements and internal latches and wherein said boundary latches mark the boundaries of said blocks.
3. The design structure according to claim 2 , wherein said internal latches comprises said non-primary inputs and said non-primary outputs.
4. The design structure according to claim 2 , wherein said boundary latches comprise said primary inputs and said primary outputs.
5. The design structure according to claim 2 , further comprising a controller connected to blocks to control said boundary latches by said root clock signal.
6. The design structure according to claim 2 , further comprising a controller connected to blocks to control said internal latches by said sub-domain clock signal.
7. The design structure according to claim 1 , wherein said design structure comprises a netlist which describes a circuit.
8. The design structure according to claim 1 , wherein said design structure resides on a storage non-transient medium as a data format used for the exchange of layout data of integrated circuits.
9. The design structure according to claim 1 , wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.
10. A design structure embodied in a machine readable non-transient medium used in a design process, the design structure comprising a system for noise reduction in an electrical circuit comprising:
a synthesizer to synthesize blocks comprising sequential elements in said electrical circuit;
a generator to operate on said sequential elements to generate a root clock signal and at least one phase-shifted sub-domain clock signal for each of said blocks;
a first assignment unit to act on said blocks to assign primary inputs and primary outputs of said block to said root clock signal;
a second assignment unit to act on said blocks to assign non-primary inputs and non-primary outputs of said block assigned to said phase-shifted sub-domain clock signal;
an allocator connected to said generator to allocate said blocks comprising different phase-shifted sub-domain clock signals, and
wherein said sequential elements comprise boundary latches and internal latches and wherein said boundary latches mark the boundaries of said blocks.
11. The design structure according to claim 10 , wherein said internal latches comprises said non-primary inputs and said non-primary outputs.
12. The design structure according to claim 10 , wherein said boundary latches comprise said primary inputs and said primary outputs.
13. The design structure according to claim 10 , further comprising a controller connected to blocks to control said boundary latches by said root clock signal.
14. The design structure according to claim 10 , wherein said design structure comprises a netlist which describes a circuit.
15. The design structure according to claim 10 , wherein said design structure resides on a storage non-transient medium as a data format used for the exchange of layout data of integrated circuits.
16. The design structure according to claim 10 , wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.
17. A design structure embodied in a machine readable non-transient medium used in a design process, the design structure comprising a system for noise reduction in an electrical circuit comprising:
a synthesizer to synthesize blocks comprising sequential elements in said electrical circuit, wherein said sequential elements comprise boundary latches and wherein said boundary latches mark the boundaries of said blocks;
a generator to operate on said sequential elements to generate a root clock signal and at least one phase-shifted sub-domain clock signal for each of said blocks;
a first assignment unit to act on said blocks to assign primary inputs and primary outputs of said block to said root clock signal;
a second assignment unit to act on said blocks to assign non-primary inputs and non-primary outputs of said block assigned to said phase-shifted sub-domain clock signal;
an allocator connected to said generator to allocate said blocks comprising different phase-shifted sub-domain clock signals; and
a controller connected to blocks to control said boundary latches by said root clock signal.
18. The design structure according to claim 17 , wherein said design structure comprises a netlist which describes a circuit.
19. The design structure according to claim 17 , wherein said design structure resides on a storage non-transient medium as a data format used for the exchange of layout data of integrated circuits.
20. The design structure according to claim 17 , wherein said design structure includes at least one of test data files, characterization data, verification data, and design specifications.