Method for noise reduction in a phase locked loop and a device having noise reduction capabilities
View Patent ↗A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.
1. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal;
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the adjusting comprises adjusting an adjustable delay circuit within a phase detector of the PLL.
2. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal:
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the adjusting comprises adjusting an adjustable trickle current source.
3. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal;
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the introducing comprises counting a frequency reduced signal.
4. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal;
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the time shift is selected in response to noise generated by components other than the PLL.
5. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal;
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period; and
an adjustable trickle current source adapted to provide an adjustable trickle current to a charge pump that is coupled between the phase detector and a loop filter.
6. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal;
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period; and
an adjustable delay circuit within a phase detector that is adapted to force the phase detector to generate control pulses even at an absence of phase difference between a reference signal and a frequency divided signal provided to the phase detector.
7. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period;
wherein the adjustable delay unit is preceded by a prescaler.
8. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal;
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period; and
additional noisy components; wherein the adjustable time shift is determined in response to the noise of at least one additional noisy components.
9. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal;
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period; and
a second PLL, wherein the time shift of the first PLL is adjusted in response to a modulation noise period of the second PLL.
10. A device comprising at least one phased locked loop the phase locked loop (PLL) comprises:
a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal;
a modulator, coupled to the frequency divider, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period;
a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal;
an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period; and
a second PLL, wherein a time shift introduced between a measurement period of the second PLL and a modulation noise period of the second PLL is responsive to the modulation noise period of the first PLL.
11. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal;
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the device comprises a second PLL and wherein the stage of adjusting is responsive to a modulation noise period of the second PLL.
12. A method for reducing noise in a device that comprises one or more phase locked loops (PLLs), the method comprises:
modulating a frequency divider, by a modulator that introduces a modulation noise within a modulation noise period, to provide a frequency divided signal;
introducing a time shift between the modulation noise period and a measurement period;
measuring, during a measurement period a difference between a reference signal and the frequency divided signal; and
adjusting at least one adjustable component of a PLL such as to determine the time shift;
wherein the device comprises a second PLL and wherein a stage of adjusting a time shift of the second PLL is responsive to a modulation noise period of the first PLL.