IP Library Granted Patent US 7,727,876
Granted Patent B2
US 7,727,876 · App. 11/934,009 · Granted Jun 1, 2010

Semiconductor device and method of protecting passivation layer in a solder bump process

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Quick Facts
Patent No.
US 7,727,876
App. No.
11/934,009
Granted
Jun 1, 2010
Kind
B2
Abstract

A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

Claims (51)

1. A method of making a semiconductor device, comprising:

providing a substrate having a plurality of active devices formed thereon;

forming a contact pad on the substrate in electrical contact with the plurality of active devices;

disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad;

forming a passivation layer over the substrate and intermediate conduction layer;

forming an adhesive layer substantially covering over the passivation layer;

forming a barrier layer over the adhesive layer;

forming a wetting layer over the barrier layer;

removing the barrier layer and wetting layer in a first region while maintaining the barrier layer, wetting layer, and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;

patterning a dry film over the adhesive layer in the first region;

depositing bump material over the wetting layer, barrier layer, and adhesive layer in the second region in areas between the dry film;

reflowing the bump material to form interconnect bumps, wherein the adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps; and

removing the dry film.

2. The method of claim 1 , further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.

3. The method of claim 1 , wherein the wetting layer, barrier layer and adhesive layer constitute an under bump metallization structure.

4. The method of claim 1 , wherein the adhesive layer follows a contour of the passivation layer.

5. The method of claim 1 , wherein the adhesive layer is made with a material selected from the group consisting of titanium, aluminum, titanium tungsten, and chromium.

6. A method of making a semiconductor device, comprising:

providing a substrate having a plurality of active devices formed thereon;

forming a contact pad on the substrate in electrical contact with the plurality of active devices;

forming a passivation layer over the substrate;

forming an adhesive layer over the passivation layer;

forming a wetting layer over the adhesive layer;

removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;

patterning a dry film over the adhesive layer in the first region;

depositing bump material over the wetting layer and adhesive layer in the second region in areas between the dry film;

reflowing the bump material to form interconnect bumps, wherein the adhesive layer substantially covering the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps; and

removing the dry film.

7. The method of claim 6 , further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.

8. The method of claim 6 , further including disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad.

9. The method of claim 6 , further including forming a barrier layer between the adhesive layer and the wetting layer.

10. The method of claim 6 , wherein the wetting layer and adhesive layer constitute an under bump metallization structure.

11. The method of claim 6 , wherein the adhesive layer follows a contour of the passivation layer.

12. A method of making a semiconductor device, comprising:

providing a substrate having a plurality of active devices formed thereon;

forming a contact pad on the substrate in electrical contact with the plurality of active devices;

forming a passivation layer over the substrate;

forming an adhesive layer over the passivation layer;

forming a wetting layer over the adhesive layer;

removing the wetting layer in a first region while maintaining the wetting layer and adhesive layer in a second region and maintaining the adhesive layer over the passivation layer in the first region;

depositing bump material over the wetting layer and adhesive layer in the second region; and

reflowing the bump material to form interconnect bumps, wherein the adhesive layer over the passivation layer reduces cracking in the passivation layer during formation of the interconnect bumps.

13. The method of claim 12 , further including removing the adhesive layer in the first region after reflowing the solder material to form the interconnect bumps.

14. The method of claim 12 , further including disposing an intermediate conduction layer above the substrate in electrical contact with the contact pad.

15. The method of claim 12 , further including forming a barrier layer between the adhesive layer and the wetting layer.

16. The method of claim 12 , further including:

patterning a dry film over the adhesive layer in the first region prior to the step of depositing solder material over the wetting layer and adhesive layer in the second region; and

removing the dry film after the step of depositing solder material over the wetting layer and adhesive layer in the second region.

17. The method of claim 12 , wherein the wetting layer and adhesive layer constitute an under bump metallization structure.

18. The method of claim 12 , wherein the adhesive layer follows a contour of the passivation layer.

19. The method of claim 12 , wherein the adhesive layer is made with a material selected from the group consisting of titanium, aluminum, titanium tungsten, and chromium.

Assignments (6)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 038378 FRAME: 0328 Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064838/0948 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0328 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2007
From: LIN, YAOJIAN; CAO, HAIJING; ZHANG, QING
To: STATS CHIPPAC, LTD.
Reel/Frame 020123/0691 →