IP Library Granted Patent US 7,659,743
Granted Patent B2
US 7,659,743 · App. 11/947,206 · Granted Feb 9, 2010

Method and apparatus for testing electronic components within horizontal and vertical boundary lines of a wafer

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,659,743
App. No.
11/947,206
Granted
Feb 9, 2010
Kind
B2
Abstract

A method and an apparatus are provided which make it possible, when testing chips arranged on a wafer, to be able to test optionally both additional components arranged on horizontal boundary lines and on vertical boundary lines. The additional components arranged on horizontal boundary lines are tested in a first position of the wafer. For testing the additional components arranged on vertical boundary lines, the wafer is rotated about its vertical axis through 90° relative to the first position into a second position. The apparatus comprises a housing and, in the housing, at least one test probe for making contact with an electronic component, a chuck for moving the wafer and a rotatably mounted additional plate operatively connected to the chuck.

Claims (14)

1. A method for testing electronic components on a wafer, the method comprising:

providing a chuck and an additional plate operatively coupled thereto for rotating the wafer about its vertical axis through 90° relative to a first position into a second position, wherein without the operatively coupled additional plate, the chuck is rotatable less than 90° only;

testing electronic components arranged on one of horizontal boundary lines or vertical boundary lines in the first position of the wafer;

rotating the wafer about its vertical axis through 90° relative to the first position into a second position; and

testing additional electronic components arranged on the other of the horizontal boundary lines and the vertical boundary lines of the wafer.

2. The method according to claim 1 , wherein the rotation of the wafer is effected in a plurality of steps, wherein the wafer is raised during each step and lowered between two respective steps.

3. An apparatus for testing electronic components on a wafer, comprising:

at least one test probe adapted to make contact with and test an electronic component arranged in one of a horizontal boundary line or a vertical boundary line of the wafer in a first position of the wafer;

a chuck and an additional plate operatively coupled thereto for rotating the wafer about its vertical axis through 90° relative to the first position into a second position, wherein without the operatively coupled additional plate, the chuck is rotatable less than 90° only:

wherein the at least one test probe is adapted to make contact with and test an additional component arranged on the other of the horizontal boundary line and the vertical boundary line of the wafer when the wafer is in the second position.

4. The apparatus according to claim 3 , wherein the additional plate has a drive device for rotating the additional plate about a vertical axis of the additional plate.

5. The apparatus according to claim 4 , wherein the additional plate is arranged on the chuck and has fixing means for fixing the wafer on a surface of the additional plate.

6. The apparatus according to claim 3 , wherein a bracket surrounds the chuck, and wherein the additional plate bears on the chuck in a raised position of the chuck and bears on the bracket in a lowered position of the chuck.

7. The apparatus according to claim 6 , wherein the additional plate has a bearing collar, with which the additional plate bears on the bracket in the lowered position of the chuck.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2025
From: HSBC BANK USA, NATIONAL ASSOCIATION
To: FORMFACTOR, INC.
Reel/Frame 072853/0001 →
SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS Recorded Jul 12, 2016
From: FORMFACTOR, INC.; ASTRIA SEMICONDUCTOR HOLDINGS, INC.; CASCADE MICROTECH, INC.; MICRO-PROBE INCORPORATED
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039184/0280 →
MERGER Recorded May 9, 2011
From: SUSS MICROTEC TEST SYSTEMS GMBH
To: CASCADE MICROTECH, INC.
Reel/Frame 026246/0706 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2008
From: KANEV, STOJAN; KIESEWETTER, JORG
To: SUSS MICROTEC TEST SYSTEMS GMBH
Reel/Frame 020471/0767 →