Reduced state quadbit
View Patent ↗A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.
1. A memory device comprising:
at least one memory cell element-pair of a multi-level flash memory array, the memory cell element-pair comprising first and second elements, each element configured to store one of a blank level and two or more program levels; and
a component configured to store in the at least one memory cell element-pair a program pattern of a plurality of program pattern combinations, comprising:
two blank levels;
two program levels; and
one blank level and one program level, the levels differing by less than a predetermined value and configured to exclude from the storing, program pattern combinations having levels differing by the predetermined value or greater without replacing the excluded program pattern combinations with other combinations.
2. The memory device of claim 1 , wherein the predetermined value corresponds to a maximum allowable difference between the corresponding threshold voltages of the blank level and the program level.
3. The memory device of claim 1 , wherein the levels differing by less than a predetermined value corresponds to a difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
4. The memory device of claim 1 , wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells.
5. The memory device of claim 1 , wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells, and wherein the blank level and the two or more program levels correspond to three or more threshold voltages and three or more data states per element.
6. The memory device of claim 5 , wherein the two or more program levels comprise three program levels, and wherein the predetermined value is 3, whereby the program pattern combinations comprise: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, 31, and 13, but exclude the 41 and 14 combinations.
7. A method of forming a memory device comprising:
forming at least one memory cell of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels; and
excluding one or more program pattern combinations that can be stored in the two or more memory elements of the at least one memory cell without replacing the excluded one or more program pattern combinations with other combinations.
8. The method of claim 7 , wherein the memory cell comprises a memory cell element-pair comprising a first element and a second element, each element configured to store a blank level and two or more program levels.
9. The method of claim 8 , wherein the excluding one or more program pattern combinations that can be stored in the at least one memory cell element-pair comprises restricting the program pattern combinations which may be stored to a set, comprising:
two blank levels;
two program levels; and
one blank level and one program level, wherein the difference between the corresponding threshold voltages of the blank level and the program level is less than a difference threshold voltage and excluding from the programming, pattern combinations having threshold voltages differing by the difference threshold voltage or greater without replacing the excluded one or more program pattern combinations with other combinations.
10. The method of claim 9 , wherein the difference threshold voltage is a maximum allowable voltage difference between the corresponding threshold voltages of the blank level and the program level.
11. The method of claim 9 , wherein the difference threshold voltage is the difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
12. A method of programming memory cell element-pairs of a multi-level flash memory array, each element of the element-pairs configured to store one of a blank level and two or more program levels, the method comprising:
providing two or more unprogrammed memory cell element-pairs; and
programming one or more of the memory cell element-pairs to one of a plurality of program pattern combinations, comprising:
two blank levels;
two program levels; and
one blank level and one program level, wherein the difference between the corresponding threshold voltage of the blank level and the program level is less than a difference threshold voltage and excluding from the programming, program pattern combinations having threshold voltages differing by the difference threshold voltage or greater without replacing the excluded program pattern combinations with other combinations.
13. The method of claim 12 , wherein the difference threshold voltage corresponds to a maximum allowable threshold voltage difference between a first element of the element-pair from the blank level, when a second element of the element-pair is programmed to one of the two or more program levels.
14. The method of claim 12 , further comprising excluding one or more of the program pattern combinations that can be stored in the at least one memory cell based on selecting only those pattern combinations that correspond to threshold voltages of the blank level and the program level that differ by less than the difference threshold voltage.
15. The method of claim 12 , wherein the plurality of program patterns comprise four or more program patterns.
16. The method of claim 12 , wherein the difference threshold voltage is the difference between the threshold voltage of the program level of the first element and the threshold voltage of the blank level of the second element.
17. The method of claim 12 , wherein the blank level and two or more program levels correspond to three or more threshold voltages.
18. The method of claim 17 , wherein the memory cells of the multi-level flash memory array comprise dual element nitride storage flash memory cells, and wherein the three or more threshold voltages correspond to three or more data states per bit or element.
19. The method of claim 12 , wherein the two or more program levels comprise three program levels, and wherein the difference threshold voltage restricts the program pattern combinations to: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, 31, and 13, but exclude the 41 and 14 combinations.
20. The method of claim 12 , wherein the two or more program levels comprise three program levels, and wherein the difference threshold voltage restricts the program pattern combinations to: 11, 22, 23, 24, 32, 33, 34, 42, 43, 44, 21, 12, but exclude the 31, 13, 41 and 14 combinations.