Granted Patent B2

US 7,902,051 · App. 11/970,100 · Granted Mar 8, 2011

Abstract

Claims (32)

1. A method of producing a PN junction comprising:

providing a single crystal substrate;

forming an insulating layer on the single crystal substrate;

forming a via through the insulating layer to provide an exposed portion of the single crystal substrate;

depositing an amorphous Si-containing material by chemical vapor deposition at a temperature of less than 500° C. on at least the exposed portion of the single crystal substrate;

forming a dielectric cap layer encapsulating the amorphous Si-containing material within the insulating layer;

converting at least a portion of the amorphous material into a single crystal material by increasing a temperature of the at least a portion of the amorphous Si-containing material by laser annealing or electron beam annealing the amorphous material through the dielectric cap layer to a temperature greater than a melting temperature of the amorphous Si-containing material and less than a melting temperature of the single crystal substrate; and

forming a first dopant region abutting a second dopant region in the single crystal material after the converting of the amorphous material into the single crystal material.

2. The method of claim 1 , wherein the single crystal material is single crystal Si-containing material.

3. The method of claim 2 , wherein the amorphous Si-containing material comprises amorphous Si or amorphous SiGe, and the single crystal Si-containing material comprises single crystal Si or single crystal SiGe.

4. The method of claim 1 , wherein the single crystal substrate comprises Si having a <100>, <111>, or <110>crystal orientation.

5. The method of claim 1 , wherein the laser annealing or the electron beam annealing further comprises a single or a series of pulses of about 10 nano-seconds (ns) to about 50 nano-seconds (ns).

6. The method of claim 2 , wherein the increasing of the temperature of the at least the portion of the amorphous Si-containing material comprises increasing the temperature to greater than 1150° C.

7. The method of claim 1 , wherein the forming of the first dopant region in the single crystal material comprises implanting a P-type dopant and the forming of the second dopant region comprises implanting an N-type dopant.

8. The method of claim 1 , further comprising forming an oxide atop the amorphous Si-containing material prior to forming the single crystal Si.

9. The method of claim 1 , wherein the PN junction is integrated with resistive memories, phase change memory devices, or a combination thereof.

10. A method of producing a memory device comprising:

providing a single crystal substrate;

depositing an amorphous Si-containing material by chemical vapor deposition at a temperature of 500° C. on at least a portion of the single crystal substrate;

forming a dielectric cap layer over an entire upper surface of the amorphous Si-containing layer; converting at least a portion of the amorphous material into a single crystal material by laser annealing or electron beam annealing the amorphous material through the dielectric cap layer to increase a temperature of the at least the portion of the amorphous Si-containing material to a temperature greater than a melting temperature of the amorphous Si-containing material and less than a melting temperature of the single crystal substrate;

forming a PN junction by implanting a dopant region in the single crystal material; and

forming a memory cell in contact with the PN junction.

11. The method of claim 10 , wherein the forming of the memory cell comprises:

forming a silicide contact on a dopant region of the PN junction;

forming an electrode atop the silicide contact; and

forming a phase change memory material atop the electrode.

12. The method of claim 10 further comprising forming an insulating layer on the single crystal substrate and forming a via through the insulating layer to expose the portion of single crystal substrate that the amorphous Si-containing material is present on, wherein the step of the forming of the amorphous Si-containing material substantially fills the via with the amorphous Si-containing material.

13. The method of claim 10 further comprising forming a barrier metal atop the phase change memory material and etching the barrier metal and phase change memory material to provide a barrier metal/phase change memory material stack.

14. The method of claim 13 , wherein forming the electrode comprises:

recessing the single crystal Si below the upper surface of the insulating layer to expose sidewalls of the via;

forming spacers on the sidewalls of the via; and

depositing a barrier metal in the via atop the silicide contact.

Assignments (10)