Method of forming a charge pump controller and structure therefor

1. A switched capacitor controller comprising:

a first MOS transistor having a first portion that includes a first gate and having a second portion that includes a second gate, the first gate configured to form a first on-resistance of the first MOS transistor, the second gate configured to form a second on-resistance for the first MOS transistor that is less than the first on-resistance, the first MOS transistor configured to couple a pump capacitor to receive a first current to charge the pump capacitor;

a second MOS transistor having a first portion that includes a first gate and a having a second portion that includes a second gate, the first gate configured to form a first on-resistance of the second MOS transistor, the second gate configured to form a second on-resistance for the second MOS transistor that is less than the first on-resistance, the second MOS transistor configured to couple the pump capacitor to provide a second current to a load;

a first circuit configured to enable the first portion of the first MOS transistor but not the second portion of the first MOS transistor to charge the pump capacitor responsively to a first voltage on one of the pump capacitor or a load capacitor being no greater than a first value;

the first circuit configured to enable the first portion of the second MOS transistor but not the second portion of the second MOS transistor to provide the second current to the load responsively to the first voltage being no greater than the first value;

the first circuit configured to enable the first and second portions of the first MOS transistor responsively to the first voltage being no less than the first value; and

the first circuit configured to enable the first and the second portions of the second MOS transistor responsively to the first voltage being no less than the first value.

2. The switched capacitor controller of claim 1 wherein the first circuit includes a comparator configured to compare the voltage on one of the pump capacitor or the load capacitor to a reference voltage.

3. The switched capacitor controller of claim 1 wherein the first circuit is configured to enable the first MOS transistor and the second MOS transistor out of phase with each other.

4. The switched capacitor controller of claim 1 further including a third transistor that is enabled responsively to enabling the first MOS transistor, the third transistor configured to couple one terminal of the pump capacitor to a charging voltage and the first MOS transistor configured to couple a second terminal of the pump capacitor to a voltage return.

5. The switched capacitor controller of claim 1 further including a fourth transistor that is enabled responsively to enabling the second MOS transistor, the fourth transistor configured to couple one terminal of the pump capacitor to an output of the switched capacitor controller and the second MOS transistor configured to couple a second terminal of the pump capacitor to receive an input voltage of the switched capacitor controller.

6. The switched capacitor controller of claim 1 wherein the first on-resistance of the first MOS transistor is greater than approximately ten times the second on-resistance of the first MOS transistor.

7. The switched capacitor controller of claim 1 wherein the first on-resistance of the second MOS transistor is greater than approximately ten times the second on-resistance of the second MOS transistor.

8. The switched capacitor controller of claim 1 wherein the first portion and the second portion of the first MOS transistor share common source and common drain regions and separate gate and channel regions.

9. The switched capacitor controller of claim 1 wherein the first MOS transistor formed as a cell based transistor.

10. A method of forming a switch for a switched capacitor controller comprising:

forming a first MOS transistor with a first portion having a first gate that provides the first MOS transistor a first on-resistance responsively to enabling the first portion and with a second portion having a second gate that provides the first MOS transistor a second on-resistance responsively to enabling the second portion; and

coupling the first MOS transistor to operably switch a pump capacitor to receive a first current to charge the pump capacitor.

11. The method of claim 10 further including configuring a control circuit to enable the first portion of the first MOS transistor and not enable the second portion of the first MOS transistor responsively to a voltage on one of the pump capacitor or on a load capacitor being no greater than a first value.

12. The method of claim 10 further including forming a second MOS transistor with a first portion having a first gate that provides the second MOS transistor a first on-resistance responsively to enabling the first portion and with a second portion having a second gate that provides the second MOS transistor a second on-resistance responsively to enabling the second portion; and

coupling the second MOS transistor to operably switch the pump capacitor to provide a second current from the pump capacitor to a load.

13. The method of claim 12 further including configuring a control circuit to enable the first portion of the first MOS transistor and the first portion of the second MOS transistor but not enable the second portion of the first MOS transistor and not enable the second portion of the second MOS transistor responsively to a voltage on one of the pump capacitor or a load capacitor being no greater than a first value.

14. The method of claim 10 wherein forming the first MOS transistor with the first portion includes forming the first portion and the second portion to have a common source region and a common drain region but separate channel and gate regions and further including forming the first on-resistance to be at least ten times the second on-resistance.