Low power mode fault recovery method, system and apparatus
View Patent ↗A semiconductor integrated circuit device uses two keeper cells per configuration and/or enable bit as dual redundant storage with error detection thereof. One of the two keeper cells stores a logic level and the other keeper cell stores the inverse of that logic level before the integrated circuit device goes into a low power mode. An exclusive OR (XOR) is performed on the outputs of the two keeper cells (a keeper cell pair) such that if the two keeper cells of the keeper cell pair do not have opposite logic levels stored therein, then the respective XOR outputs an error signal for that keeper cell pair and the error signal is used to force the integrated circuit device out of the low power mode, depending on software control, with or without disturbing input-output (I/O) configuration control and data states present at the time the low power mode was entered.
1. An integrated circuit device having a low power mode, comprising:
power controllable circuits;
power control for the power controllable circuits, wherein the power control causes the power controllable circuits to go into and return from a low power mode;
at least one keeper cell pair coupled between the power controllable logic and the power control, wherein the at least one keeper cell pair has continuous error detection; and
the at least one keeper cell pair stores one bit of configuration information for the power control for each one of the at least one keeper cell pair when the power controllable circuits are in the low power mode;
wherein if an error is detected for the configuration information stored in the at least one keeper cell pair an error signal is generated that forces the power control to return the power controllable circuits from the low power mode to a predefined error exit mode for handling the detected error.
2. The integrated circuit device according to claim 1 , wherein the at least one keeper cell pair having error detection comprises:
a first keeper cell that stores a non-inverted configuration information bit;
a second keeper cell that stores an inverted configuration information bit; and
a comparison circuit for determining whether the first and second keeper cells have outputs at substantially the same logic level, wherein the error signal is generated if the first and second keeper cell outputs are at substantially the same logic level.
3. The integrated circuit device according to claim 1 , wherein the the predefined error exit mode comprises predefined forced configuration information for the power control.
4. The integrated circuit device according to claim 1 , wherein the at least one keeper cell pair are a plurality of keeper cell pairs storing an enable and the configuration information for the power control when the power controllable logic is in the low power mode.
5. The integrated circuit device according to claim 3 , wherein the power control stores the predefined forced configuration information that is used to configure operation of the power control when the error is detected.
6. The integrated circuit device according to claim 5 , wherein the predefined forced configuration information is stored in a non-volatile memory.
7. The integrated circuit device according to claim 1 , wherein the low power mode is a deep sleep mode.
8. The integrated circuit device according to claim 7 , wherein the power control is a deep sleep watchdog timer.
9. The integrated circuit device according to claim 1 , wherein the power controllable circuits comprise both digital logic and analog circuits.
10. The integrated circuit device according to claim 1 , further comprising at least one timer coupled to the at least one keeper cell pair.
11. The integrated circuit device according to claim 1 , further comprising at least one counter coupled to the at least one keeper cell pair.
12. The integrated circuit device according to claim 1 , further comprising logic coupled to the at least one keeper cell pair.
13. A method for insuring recovery from a low power mode of an integrated circuit device, said method comprising the steps of:
entering a low power mode;
storing configuration information for controlling a low power mode of power controllable circuits an integrated circuit device in at least on keeper cell pair;
continuously detecting when the stored configuration information in the at least one keeper cell pair is corrupted; and
forcing recovery of the power controllable circuits of the integrated circuit device from the low power mode to a predefined error exit mode upon detection of corrupted stored configuration information in the at least one keeper cell pair.
14. The method according to claim 13 , wherein the step of storing configuration information comprises the steps of:
storing non-inverted configuration information in a one of the at least one keeper cell pair; and
storing inverted configuration information in an other one of the at least one keeper cell pair.
15. The method according to claim 13 , wherein the step of detecting when the stored configuration information is corrupted comprises the steps of:
comparing the storing non-inverted configuration information with the inverted configuration information;
generating an error signal if any respective ones of the non-inverted configuration information and the inverted configuration information are at substantially the same logic level.
16. The method according to claim 13 , wherein the step of forcing recovery of the power controllable circuits of the integrated circuit device from the low power mode upon detection of corrupted stored configuration information comprises the steps of:
forcing use of recovery configuration information; and
returning the power controllable circuits of the integrated circuit device from the low power mode by using the forced recovery information.
17. The integrated circuit device according to claim 13 , wherein the low power mode is a deep sleep mode.