Granted Patent B2

US 7,785,973 · App. 12/020,316 · Granted Aug 31, 2010

Assignee: Spansion LLC

Abstract

Claims (46)

1. A process of forming an electronic device comprising:

forming a semiconductor layer over a substrate having a primary surface, wherein the semiconductor layer has a first conductivity type;

selectively doping a region of the semiconductor layer to form a first doped region having a second conductivity type opposite that of the first conductivity type; and

patterning the semiconductor layer to form a gate electrode that includes a first portion and a second portion, wherein the first portion includes a portion of the first doped region, and the second region includes a portion of the semiconductor layer outside of the first doped region;

wherein:

selectively doping the region of the semiconductor layer comprises selectively doping another region of the semiconductor layer to form a second doped region having the second conductivity type; and

patterning the semiconductor layer to form the gate electrode is performed such that the gate electrode further includes a third portion, wherein the third portion includes a portion of the second doped region, and the second portion of the gate electrode is disposed between the first and third portions of the gate electrode;

forming a first patterned mask layer over the semiconductor layer before selectively doping the semiconductor layer; and

wherein selectively doping the semiconductor layer comprises ion implanting the semiconductor layer, wherein ions during ion implanting are directed towards the semiconductor layer at an angle greater than 8° from a direction perpendicular to the primary surface.

2. The process of claim 1 , further comprising:

forming a gate dielectric layer over the substrate;

forming a charge storage layer over the gate dielectric layer; and

forming source/drain regions within the substrate after forming the gate electrode.

3. The process of claim 2 , further comprising:

forming a conductive layer over the gate electrode; and

patterning the conductive layer to forming a conductive member, wherein a word line comprises the conductive member and the gate electrode.

4. The process of claim 1 , further comprising forming a spacer adjacent to an edge of a feature within the patterned first mask layer after selectively doping the substrate and before patterning the semiconductor layer.

5. The process of claim 4 , wherein patterning the semiconductor layer comprises selectively etching the semiconductor layer after forming the spacer.

6. The process of claim 5 , further comprising forming a second patterned mask layer, wherein:

forming the first patterned mask layer comprises:

forming a mask layer after forming the semiconductor layer and before forming the second patterned mask layer; and

selectively etching the mask layer while the second patterned mask layer overlies the mask layer to form the first patterned mask layer before selectively etching the semiconductor layer.

7. The process of claim 6 , further comprising:

removing the second patterned mask layer after forming the first patterned mask layer; and

annealing the semiconductor layer after removing the second patterned mask layer and before patterning the semiconductor layer.

8. A process of forming an electronic device comprising:

forming a gate dielectric layer over a substrate having a primary surface;

forming a charge storage layer over the gate dielectric layer, wherein the charge storage layer comprises a nitride layer;

forming a semiconductor layer over the charge storage layer;

doping the semiconductor layer with a dopant having a first conductivity type;

forming a first patterned mask layer over the semiconductor layer;

ion implanting the semiconductor layer at an angle greater than 8° from a direction perpendicular to the primary surface to form a first doped region and a second doped region, wherein each of the first and second doped regions has a second conductivity type opposite that of the first conductivity type;

patterning the semiconductor layer to form gate electrodes that each include a first portion, a second portion, and a third portion, wherein:

the first portion includes a portion of the first doped region;

the second portion includes a portion of the semiconductor layer outside of the first and second doped regions; and

the third portion includes a portion of the second doped region;

forming source/drain regions within the substrate after patterning the semiconductor layer;

forming an insulating layer over the gate electrode and the source/drain regions;

removing a portion of the insulating layer overlying the gate electrodes;

forming a conductive layer over the gate electrodes; and

patterning the conductive layer to form conductive members that are electrically connected to the first and third portions of the gate electrodes, wherein word lines include the conductive members and the gate electrodes.

9. The process of claim 8 , wherein ion implanting the semiconductor layer comprises:

ion implanting for a first time at a first angle greater than 8° from the direction perpendicular to the primary surface;

rotating the substrate; and

ion implanting for a second time at a second angle greater than 8° from the direction perpendicular to the primary surface during or after rotating the substrate.

10. The process of claim 8 , further comprising forming spacers adjacent to edges of features within the patterned first mask layer after selectively doping the substrate and before patterning the semiconductor layer.

Assignments (9)

Continuity (1)