Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
View Patent ↗A packaged light emitting device includes a carrier substrate having a top surface and a bottom surface, first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate, and a bond pad on the top surface of the substrate in electrical contact with the first conductive via. A diode having first and second electrodes is mounted on the bond pad with the first electrode is in electrical contact with the bond pad. A passivation layer is formed on the diode, exposing the second electrode of the diode. A conductive trace is formed on the top surface of the carrier substrate in electrical contact with the second conductive via and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode.
1. A semiconductor structure, comprising:
a carrier substrate having a top surface and a bottom surface;
a wafer including a plurality of light emitting diodes thereon, wherein the light emitting diodes on the wafer are bonded to the top surface of the carrier substrate between the wafer and the carrier substrate, each of the light emitting diodes having first and second electrodes; and
a plurality of pairs of first and second conductive vias extending from the top surface of the carrier substrate to the bottom surface of the carrier substrate, wherein at least one via of each pair of conductive vias is electrically connected to the first electrode of a light emitting diode of the plurality of light emitting diodes.
2. The semiconductor structure of claim 1 , further comprising:
a plurality of bond pads disposed between the top surface of the carrier substrate and the plurality of light emitting diodes, wherein at least one of the plurality of light emitting diodes is mounted on one of the plurality of bond pads.
3. The semiconductor structure of claim 1 , further comprising:
a plurality of bond pads on the bottom surface of the carrier substrate, wherein each of the plurality of bond pads on the bottom surface of the carrier substrate is in electrical contact with at least one of the first or second conductive vias.
4. The semiconductor structure of claim 1 , wherein respective ones of the first and second conductive vias are isolated from others of the first and second conductive vias.
5. The semiconductor structure of claim 1 , wherein the wafer comprises an epiwafer and the light emitting diodes comprise epitaxial growth layers on the epiwafer.
6. The semiconductor structure of claim 1 , wherein the first and second electrodes comprise metal electrodes.
7. A packaged light emitting device, comprising:
a carrier substrate having a top surface and a bottom surface;
first and second conductive vias extending from the top surface of the substrate to the bottom surface of the substrate;
a bond pad on the top surface of the substrate and in electrical contact with the first conductive via;
a diode having first and second electrodes on opposite sides of the diode, wherein the diode is mounted on the bond pad, and wherein the first electrode is in electrical contact with the bond pad;
a passivation layer on the top surface of the carrier substrate and in contact with at least one sidewall of the diode;
a conductive trace on the top surface of the carrier substrate, wherein the conductive trace is on the passivation layer and electrically connects the second conductive via and the second electrode;
a reflective layer on the top surface of the carrier substrate, the reflective layer surrounding the diode and defining a cavity above the diode, wherein the reflective layer is at least partially on the passivation layer; and
an encapsulant material in the cavity.
8. The packaged light emitting device of claim 7 , further comprising a transparent sealing layer on the reflective layer above the diode, wherein the sealing layer forms a hermetic seal to the reflective layer.